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* score: Add _CPU_Get_TLS_thread_pointer()Sebastian Huber2023-09-151-0/+7
| | | | | | | | Add _CPU_Get_TLS_thread_pointer() to get the thread pointer which is used to get the address of thread-local storage objects associated with a thread. Update #4920.
* score: Remove CPU port specific cpuatomic.hSebastian Huber2023-06-121-31/+0
| | | | | All CPU ports used the same <rtems/score/cpustdatomic.h> header file to provide the atomic operations. Remove the header file indirection.
* Update company nameSebastian Huber2023-05-2010-10/+10
| | | | | The embedded brains GmbH & Co. KG is the legal successor of embedded brains GmbH.
* cpukit: Change license to BSD-2 for files with Gaisler copyrightDaniel Cederman2022-11-141-3/+22
| | | | | | | | | This patch changes the license to BSD-2 for all source files where the copyright is held by Aeroflex Gaisler, Cobham Gaisler, or Gaisler Research. Some files also includes copyright right statements from OAR and/or embedded Brains in addition to Gaisler. Updates #3053.
* riscv: Simplify _CPU_ISR_Set_level()Sebastian Huber2022-11-091-15/+13
| | | | | | | Where CPU_ENABLE_ROBUST_THREAD_DISPATCH == TRUE, the only supported interrupt level allowed to set is 0 (interrupts enabled). This constraint is enforced by the API level functions which return an error status for other interrupt levels.
* riscv: Remove superfluous init/fini functionsSebastian Huber2022-11-091-12/+0
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* riscv: Move functions to avoid build issuesSebastian Huber2022-10-141-0/+10
| | | | | The _RISCV_Map_cpu_index_to_hardid() and _RISCV_Map_hardid_to_cpu_index() functions must be available to all riscv BSPs.
* score: Add CPU_THREAD_LOCAL_STORAGE_VARIANTSebastian Huber2022-10-142-1/+3
| | | | Update #3835.
* bsps/riscv: Add Microchip PolarFire SoC BSP variantPadmarao Begari2022-09-202-2/+2
| | | | | | | | The Microchip PolarFire SoC support is implemented as a riscv BSP variant to boot with any individual hart(cpu core) or SMP based on the boot HARTID configurable and support components are 4 CPU Cores (U54), Interrupt controller (PLIC), Timer (CLINT), UART.
* Do not use RTEMS_INLINE_ROUTINESebastian Huber2022-09-192-5/+5
| | | | | | | Directly use "static inline" which is available in C99 and later. This brings the RTEMS implementation closer to standard C. Close #3935.
* score: Remove _CPU_Counter_difference()Sebastian Huber2022-09-091-8/+0
| | | | | | | All CPU ports used the same _CPU_Counter_difference() implementation. Remove this CPU port interface and mandate a monotonically increasing CPU counter. Close #3456.
* score: Add _CPU_Use_thread_local_storage()Sebastian Huber2022-07-041-0/+12
| | | | | | | | | | | | At some point during system initialization, the idle threads are created. Afterwards, the boot processor basically executes within the context of an idle thread with thread dispatching disabled. On some architectures, the thread-local storage area of the associated thread must be set in dedicated processor registers. Add the new CPU port function to do this: void _CPU_Use_thread_local_storage( const Context_Control *context ) Close #4672.
* riscv: Include missing header fileSebastian Huber2022-06-241-0/+2
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* SMP: Fix start multitasking for some targetsSebastian Huber2022-03-092-0/+19
| | | | | | | | | | | | | The previous SMP multitasking start assumed that the initial heir thread of a processor starts execution in _Thread_Handler(). The _Thread_Handler() sets the interrupt state explicitly by _ISR_Set_level() before it calls the thread entry. Under certain timing conditions, processors may perform an initial context switch to a thread which already executes its thread body (see smptests/smpstart01). In this case, interrupts are disabled after the context switch on targets which do not save/restore the interrupt state during a context switch (aarch64, arm, and riscv). Close #4627.
* riscv: Use zicsr architecture extensionSebastian Huber2022-02-255-11/+46
| | | | | | | | | | This is required for ISA 2.0 support, see chapter "Zicsr", Control and Status Register (CSR) Instructions, Version 2.0 in RISC-V Instruction Set Manual, Volume I: RISC-V User-Level ISA
* build: Remove old build systemSebastian Huber2021-09-211-11/+0
| | | | | Close #3250. Close #4081.
* score: Canonicalize _CPU_Fatal_halt()Sebastian Huber2021-07-282-2/+2
| | | | | | | | Move _CPU_Fatal_halt() declaration to <rtems/score/cpuimpl.h> and make sure it is a proper declaration of a function which does not return. Fix the type of the error code. If necessary, add the implementation to cpu.c. Implementing _CPU_Fatal_halt() as a function makes it possible to wrap this function for example to fully test _Terminate().
* score: Remove processor event broadcast/receiveSebastian Huber2021-07-281-10/+0
| | | | | | Remove _CPU_SMP_Processor_event_broadcast() and _CPU_SMP_Processor_event_receive(). These functions are hard to use since they are subject to the lost wake up problem.
* score: Remove _CPU_Initialize_vectors()Sebastian Huber2021-06-241-2/+0
| | | | | | | This CPU port macro was not used. Since the _ISR_Vector_table[] is statically allocated, CPU ports could initialize this table in _CPU_Initialize() if necessary. Remove _CPU_Initialize_vectors() to simplify the CPU port interface.
* score: Add _CPU_Context_switch_no_return()Sebastian Huber2021-05-182-0/+7
| | | | | | | | | | | The __builtin_unreachable() cannot be used with current GCC versions to tell the compiler that a function does not return to the caller, see: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99151 Add a no return variant of _CPU_Context_switch() to avoid generation of dead code in _Thread_Start_multitasking() if RTEMS was built with SMP support enabled.
* rtems: Improve RTEMS_NO_RETURN attributeSebastian Huber2020-10-101-4/+2
| | | | | | | | | | | Provide RTEMS_NO_RETURN also in case RTEMS_DEBUG is defined to prevent errors like this: error: no return statement in function returning non-void [-Werror=return-type] Use C11 and C++11 standard means to declare a no-return function. Close #4122.
* score: Add CPU_USE_LIBC_INIT_FINI_ARRAYKinsey Moore2020-06-301-0/+2
| | | | | | | | This introduces the CPU_USE_LIBC_INIT_FINI_ARRAY define for use by CPU ports to determine which global constructor and destructor methods are used instead of placing architecture defines where they shouldn't be. Close #4018
* Regenerate headers.amSebastian Huber2019-11-291-0/+1
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* riscv: preliminarily support for libdlHesham Almatary2019-11-121-0/+144
| | | | Support for targets compiled with -fno-pic and -mno-relax
* doxygen: score: Add RISC-V CPU architecture groupAndreas Dachsberger2019-04-024-1/+26
| | | | Update #3706.
* score: Rename ScoreCPU Doxygen groupSebastian Huber2019-03-261-1/+1
| | | | Update #3706.
* Remove superfluous <rtems/system.h> includesSebastian Huber2019-03-141-1/+0
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* Remove explicit file names from @fileSebastian Huber2019-02-283-3/+3
| | | | | | This makes the @file documentation independent of the actual file name. Update #3707.
* riscv: Fix misaligned access in context validateSebastian Huber2019-02-021-1/+1
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* riscv: add griscv bspJiri Gaisler2019-01-221-4/+1
| | | | Update #3678.
* grlib: use cpu-independent routines for uncached accessJiri Gaisler2019-01-223-0/+83
| | | | Update #3678.
* riscv: Enable robust thread dispatchSebastian Huber2019-01-091-0/+3
| | | | | | | It must be enabled, since the context switch code does not save/restore the interrupt status. Update #3433.
* build: Include header.am in cpukit/Makefile.amSebastian Huber2018-10-102-14/+7
| | | | | Include all cpukit/*/header.am files in cpukit/Makefile.am. This gets rid of all subtree Makefile.am and the sudirs hack.
* build: Merge score/cpu/*/Makefile.amSebastian Huber2018-10-101-12/+0
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* build: Remove specialized CPPFLAGSSebastian Huber2018-10-091-1/+0
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* score: Remove CPU_PROVIDES_IDLE_THREAD_BODYSebastian Huber2018-10-051-1/+0
| | | | | | | Remove the CPU_PROVIDES_IDLE_THREAD_BODY option to avoid unnecessary conditional compilation. Close #3539.
* score: Remove CPU_PARTITION_ALIGNMENTSebastian Huber2018-08-021-2/+0
| | | | | | | | | | | | | | Use the CPU_SIZEOF_POINTER alignment instead. The internal alignment requirement is defined by the use of Chain_Node (consisting of two pointers) to manage the free chain of partitions. It seems that previously the condition CPU_PARTITION_ALIGNMENT >= sizeof(Chain_Node) was true on all CPU ports. Now, we need an additional check. Update #3482.
* riscv: Fix CPU_ALIGNMENTSebastian Huber2018-08-021-1/+3
| | | | Update #3433.
* riscv: Rework CPU counter supportSebastian Huber2018-07-274-5/+91
| | | | Update #3433.
* riscv: Add CLINT and PLIC supportSebastian Huber2018-07-251-5/+45
| | | | | | The CLINT and PLIC need some per-processor state. Update #3433.
* riscv: Use wfi instruction for idle taskSebastian Huber2018-07-252-12/+3
| | | | Update #3433.
* riscv: Rework exception handlingSebastian Huber2018-07-256-144/+54
| | | | | | | | | | | Remove _CPU_ISR_install_raw_handler() and _CPU_ISR_install_vector() functions. Applications can install an exception handler via the fatal error handler to handle synchronous exceptions. Handle interrupt exceptions via _RISCV_Interrupt_dispatch() which must be provided by the BSP. Update #3433.
* riscv: New CPU_Exception_frameSebastian Huber2018-07-254-64/+203
| | | | | | | Use the CPU_Interrupt_frame for the volatile context. Add non-volatile registers and extra state on top of it. Update #3433.
* riscv: Add exception codesSebastian Huber2018-07-251-0/+39
| | | | Update #3433.
* score: Add _CPU_Instruction_illegal()Sebastian Huber2018-07-231-0/+5
| | | | | | | | On some architectures/simulators it is difficult to provoke an exception with misaligned or illegal data loads. Use an illegal instruction instead. Update #3433.
* score: Add _CPU_Instruction_no_operation()Sebastian Huber2018-07-201-0/+5
| | | | | This helps to reduce the use of architecture-specific defines throughout the code base.
* score: Move context validation declarationsSebastian Huber2018-07-202-4/+4
| | | | | | | The context validation support functions _CPU_Context_validate() and _CPU_Context_volatile_clobber() are used only by one test program (spcontext01). Move the function declarations to the CPU port implementation header file.
* score: Remove obsolete CPU port definesSebastian Huber2018-07-201-4/+0
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* riscv: Add LADDR assembler defineSebastian Huber2018-07-062-2/+12
| | | | | | | An address must be loaded to a register according to the code model. Add LADDR define for use in assembler code. Update #3433.
* riscv: Implement CPU counterSebastian Huber2018-07-062-2/+16
| | | | Update #3433.
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