| Commit message (Collapse) | Author | Age | Files | Lines |
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For example, the QorIQ T4240 has more than 16 TLB1 entries.
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Close #4759.
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This patch changes the license to BSD-2 for all source files where the
copyright is held by Aeroflex Gaisler, Cobham Gaisler, or Gaisler Research.
Some files also includes copyright right statements from OAR and/or
embedded Brains in addition to Gaisler.
Updates #3053.
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Set the thread ID register in the CPU context.
Update #3835.
Close #4753.
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Where CPU_ENABLE_ROBUST_THREAD_DISPATCH == TRUE, the only supported interrupt
level allowed to set is 0 (interrupts enabled). This constraint is enforced by
the API level functions which return an error status for other interrupt
levels.
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The AArch64 TRM specifies that when FPCR is set to trap floating point
exceptions, the FPSR exception bits are not set. This ensures that FPSR
is updated as FENV expects even if floating point exception traps are
enabled.
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The _RISCV_Map_cpu_index_to_hardid() and _RISCV_Map_hardid_to_cpu_index()
functions must be available to all riscv BSPs.
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This avoids a pedantic warning about a zero size Context_Control_fp.
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Update #3835.
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For most CPU ports this was already the case. This makes it possible to use
the size as an object alignment using RTEMS_ALIGNED().
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The Microchip PolarFire SoC support is implemented as a
riscv BSP variant to boot with any individual hart(cpu core)
or SMP based on the boot HARTID configurable and support
components are 4 CPU Cores (U54), Interrupt controller (PLIC),
Timer (CLINT), UART.
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Directly use "static inline" which is available in C99 and later. This brings
the RTEMS implementation closer to standard C.
Close #3935.
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All CPU ports used the same _CPU_Counter_difference() implementation. Remove
this CPU port interface and mandate a monotonically increasing CPU counter.
Close #3456.
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The VRSAVE feature of the Altivec unit can be used to reduce the amount of
Altivec registers which need to be saved/restored during interrupt processing
and context switches.
In order to use the VRSAVE optimization a corresponding multilib (-mvrsave) is
required, see GCC configuration. The -mvrsave option must be added to the
ABI_FLAGS of the BSP.
Currently only the -mcpu=e6500 based QorIQ BSP support this optimization.
Update #4712.
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Added two pragmas to address, and changed the value of
AARCH64_EXCEPTION_MAKE_ENUM_64_BIT to INT_MAX because the old value was not
in range of an int.
Updates #4662
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rtl-mdreloc-aarch64.c and elf_machdep.h came from NetBSD.
Updates #4682
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This alters the AArch64 page table generation and mapping code and MMU
configuration to use page table level 0 in addition to levels 1, 2, and
3. This allows the mapping of up to 48 bits of memory space and is the
maximum that can be mapped without relying on additional processor
extensions. Mappings are restricted based on the number of physical
address bits that the CPU supports.
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This function was never actually used and is dead code.
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At some point during system initialization, the idle threads are created.
Afterwards, the boot processor basically executes within the context of an idle
thread with thread dispatching disabled. On some architectures, the
thread-local storage area of the associated thread must be set in dedicated
processor registers. Add the new CPU port function to do this:
void _CPU_Use_thread_local_storage( const Context_Control *context )
Close #4672.
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The false trigger is covered in:
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99578
GCC 11 and 12 has been patched for constant pointer casts above
4K. This code casts a constant pointer within the first 4K
page. As a result the patch disables the warning.
Updates #4662
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Sections with identical attributes may be contiguous with a respective
begin and end address which is not on a minimum region boundary. The
begin address is aligned down to the region base address. The end
address is aligned up to the region end address. Account for this in
the check for contiguous sections.
Update #4202.
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A section may span up to the end of the address range. In this case the
end address is zero. Use the base address to check if a region should
be before another region.
Update #4202.
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This file had no header, copyright, or license. Based on git history,
added appropriate copyright and license.
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These files had no file header, copyright, or license. Based on git
history, added appropriate copyright and license.
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The other ports included that architecture's version of this file from
NetBSD. This patch follows that pattern.
closes #4641
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Permission received from Anthony Green.
Updates #3053.
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Add an architecture-specific implementation for
_CPU_Get_current_per_CPU_control() to reduce overhead for getting the
current CPU's Per_CPU_Control structure.
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Fix move of regions. Allow sections to be contained in a region (may
happen due to region alignment).
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This simplifies unit testing.
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Updates #4625.
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The previous SMP multitasking start assumed that the initial heir thread of a
processor starts execution in _Thread_Handler(). The _Thread_Handler() sets
the interrupt state explicitly by _ISR_Set_level() before it calls the thread
entry. Under certain timing conditions, processors may perform an initial
context switch to a thread which already executes its thread body (see
smptests/smpstart01). In this case, interrupts are disabled after the context
switch on targets which do not save/restore the interrupt state during a
context switch (aarch64, arm, and riscv).
Close #4627.
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Updates #3053.
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Updates #3053.
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Updates #3053.
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Updates #3053.
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Updates #3053.
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Updates #3053.
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Updates #3053.
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sse_test.c was deliberarely NOT changed.
Updates #3053.
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Updates #3053.
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This is required for ISA 2.0 support, see chapter
"Zicsr", Control and Status Register (CSR) Instructions, Version 2.0
in
RISC-V Instruction Set Manual, Volume I: RISC-V User-Level ISA
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