diff options
| author | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2023-05-19 08:18:25 +0200 |
|---|---|---|
| committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2023-05-20 11:05:26 +0200 |
| commit | bcef89f2360b97005e490c92fe624ab9dec789e6 (patch) | |
| tree | 61a05a2699d86de26b84acf355d9d9ddaa3c4c5b /cpukit/score/cpu/riscv | |
| parent | bsps/microblaze: Add device tree support to GPIO (diff) | |
| download | rtems-bcef89f2360b97005e490c92fe624ab9dec789e6.tar.bz2 | |
Update company name
The embedded brains GmbH & Co. KG is the legal successor of embedded
brains GmbH.
Diffstat (limited to 'cpukit/score/cpu/riscv')
| -rw-r--r-- | cpukit/score/cpu/riscv/cpu.c | 2 | ||||
| -rw-r--r-- | cpukit/score/cpu/riscv/include/rtems/score/cpu.h | 2 | ||||
| -rw-r--r-- | cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h | 2 | ||||
| -rw-r--r-- | cpukit/score/cpu/riscv/riscv-context-initialize.c | 2 | ||||
| -rw-r--r-- | cpukit/score/cpu/riscv/riscv-context-switch.S | 2 | ||||
| -rw-r--r-- | cpukit/score/cpu/riscv/riscv-context-validate.S | 2 | ||||
| -rw-r--r-- | cpukit/score/cpu/riscv/riscv-context-volatile-clobber.S | 2 | ||||
| -rw-r--r-- | cpukit/score/cpu/riscv/riscv-counter.S | 2 | ||||
| -rw-r--r-- | cpukit/score/cpu/riscv/riscv-exception-frame-print.c | 2 | ||||
| -rw-r--r-- | cpukit/score/cpu/riscv/riscv-exception-handler.S | 2 |
10 files changed, 10 insertions, 10 deletions
diff --git a/cpukit/score/cpu/riscv/cpu.c b/cpukit/score/cpu/riscv/cpu.c index 926b2c3926..74a716a3b2 100644 --- a/cpukit/score/cpu/riscv/cpu.c +++ b/cpukit/score/cpu/riscv/cpu.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018 embedded brains GmbH + * Copyright (c) 2018 embedded brains GmbH & Co. KG * * Copyright (c) 2015 University of York. * Hesham ALmatary <hesham@alumni.york.ac.uk> diff --git a/cpukit/score/cpu/riscv/include/rtems/score/cpu.h b/cpukit/score/cpu/riscv/include/rtems/score/cpu.h index f74ce99684..e342e7d4af 100644 --- a/cpukit/score/cpu/riscv/include/rtems/score/cpu.h +++ b/cpukit/score/cpu/riscv/include/rtems/score/cpu.h @@ -4,7 +4,7 @@ */ /* - * Copyright (c) 2018 embedded brains GmbH + * Copyright (c) 2018 embedded brains GmbH & Co. KG * * Copyright (c) 2015 University of York. * Hesham Almatary <hesham@alumni.york.ac.uk> diff --git a/cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h b/cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h index ea1e139d55..47cf2e338c 100644 --- a/cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h +++ b/cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h @@ -5,7 +5,7 @@ */ /* - * Copyright (c) 2013, 2018 embedded brains GmbH + * Copyright (C) 2013, 2018 embedded brains GmbH & Co. KG * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/cpukit/score/cpu/riscv/riscv-context-initialize.c b/cpukit/score/cpu/riscv/riscv-context-initialize.c index 572dc3ede3..67998b426e 100644 --- a/cpukit/score/cpu/riscv/riscv-context-initialize.c +++ b/cpukit/score/cpu/riscv/riscv-context-initialize.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018 embedded brains GmbH + * Copyright (c) 2018 embedded brains GmbH & Co. KG * * Copyright (c) 2015 University of York. * Hesham Almatary <hesham@alumni.york.ac.uk> diff --git a/cpukit/score/cpu/riscv/riscv-context-switch.S b/cpukit/score/cpu/riscv/riscv-context-switch.S index cfaff444b0..a00c842de2 100644 --- a/cpukit/score/cpu/riscv/riscv-context-switch.S +++ b/cpukit/score/cpu/riscv/riscv-context-switch.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018 embedded brains GmbH + * Copyright (c) 2018 embedded brains GmbH & Co. KG * * Copyright (c) 2015 University of York. * Hesham ALmatary <hesham@alumni.york.ac.uk> diff --git a/cpukit/score/cpu/riscv/riscv-context-validate.S b/cpukit/score/cpu/riscv/riscv-context-validate.S index 6bdb06a15b..838803e809 100644 --- a/cpukit/score/cpu/riscv/riscv-context-validate.S +++ b/cpukit/score/cpu/riscv/riscv-context-validate.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018 embedded brains GmbH + * Copyright (c) 2018 embedded brains GmbH & Co. KG * Copyright (c) 2015 Hesham Almatary <hesham@alumni.york.ac.uk> * * Redistribution and use in source and binary forms, with or without diff --git a/cpukit/score/cpu/riscv/riscv-context-volatile-clobber.S b/cpukit/score/cpu/riscv/riscv-context-volatile-clobber.S index 628bd1a467..efea2afc72 100644 --- a/cpukit/score/cpu/riscv/riscv-context-volatile-clobber.S +++ b/cpukit/score/cpu/riscv/riscv-context-volatile-clobber.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018 embedded brains GmbH + * Copyright (c) 2018 embedded brains GmbH & Co. KG * Copyright (c) 2015 Hesham Almatary <hesham@alumni.york.ac.uk> * * Redistribution and use in source and binary forms, with or without diff --git a/cpukit/score/cpu/riscv/riscv-counter.S b/cpukit/score/cpu/riscv/riscv-counter.S index e779325b4b..96c68e6b13 100644 --- a/cpukit/score/cpu/riscv/riscv-counter.S +++ b/cpukit/score/cpu/riscv/riscv-counter.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018 embedded brains GmbH + * Copyright (c) 2018 embedded brains GmbH & Co. KG * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/cpukit/score/cpu/riscv/riscv-exception-frame-print.c b/cpukit/score/cpu/riscv/riscv-exception-frame-print.c index 897ceaf9a8..61986a8ba2 100644 --- a/cpukit/score/cpu/riscv/riscv-exception-frame-print.c +++ b/cpukit/score/cpu/riscv/riscv-exception-frame-print.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018 embedded brains GmbH + * Copyright (c) 2018 embedded brains GmbH & Co. KG * Copyright (c) 2015 Hesham Almatary <hesham@alumni.york.ac.uk> * * Redistribution and use in source and binary forms, with or without diff --git a/cpukit/score/cpu/riscv/riscv-exception-handler.S b/cpukit/score/cpu/riscv/riscv-exception-handler.S index 87a69652a4..34e7cbb0b3 100644 --- a/cpukit/score/cpu/riscv/riscv-exception-handler.S +++ b/cpukit/score/cpu/riscv/riscv-exception-handler.S @@ -7,7 +7,7 @@ */ /* - * Copyright (c) 2018 embedded brains GmbH + * Copyright (c) 2018 embedded brains GmbH & Co. KG * Copyright (c) 2015 University of York. * Hesham Almatary <hesham@alumni.york.ac.uk> |