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* cpukit: Change license to BSD-2 for files with Gaisler copyrightDaniel Cederman2022-11-142-4/+23
| | | | | | | | | This patch changes the license to BSD-2 for all source files where the copyright is held by Aeroflex Gaisler, Cobham Gaisler, or Gaisler Research. Some files also includes copyright right statements from OAR and/or embedded Brains in addition to Gaisler. Updates #3053.
* arm: Fix Armv7-M TLS supportSebastian Huber2022-11-101-1/+1
| | | | | | | Set the thread ID register in the CPU context. Update #3835. Close #4753.
* riscv: Simplify _CPU_ISR_Set_level()Sebastian Huber2022-11-091-15/+13
| | | | | | | Where CPU_ENABLE_ROBUST_THREAD_DISPATCH == TRUE, the only supported interrupt level allowed to set is 0 (interrupts enabled). This constraint is enforced by the API level functions which return an error status for other interrupt levels.
* riscv: Remove superfluous init/fini functionsSebastian Huber2022-11-091-12/+0
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* cpukit/aarch64: Emulate FPSR for FENV trapsKinsey Moore2022-11-091-0/+20
| | | | | | | The AArch64 TRM specifies that when FPCR is set to trap floating point exceptions, the FPSR exception bits are not set. This ensures that FPSR is updated as FENV expects even if floating point exception traps are enabled.
* riscv: Move functions to avoid build issuesSebastian Huber2022-10-141-0/+10
| | | | | The _RISCV_Map_cpu_index_to_hardid() and _RISCV_Map_hardid_to_cpu_index() functions must be available to all riscv BSPs.
* powerpc: Conditionally provide Context_Control_fpSebastian Huber2022-10-141-3/+6
| | | | This avoids a pedantic warning about a zero size Context_Control_fp.
* powerpc: Fix 'noreturn' function does returnSebastian Huber2022-10-141-0/+1
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* score: INTERNAL_ERROR_IDLE_THREAD_STACK_TOO_SMALLSebastian Huber2022-10-141-0/+4
| | | | | | | Ensure that the IDLE storage allocator did allocate a suffiently large area. Update #3835. Update #4524.
* config: Add CONFIGURE_IDLE_TASK_STORAGE_SIZESebastian Huber2022-10-143-31/+95
| | | | | | | | | | | | By default, allocate the IDLE task storage areas from the RTEMS Workspace. This avoids having to estimate the thread-local storage size in the default configuration. Add the application configuration option CONFIGURE_IDLE_TASK_STORAGE_SIZE to request a static allocation of the task storage area for IDLE tasks. Update #3835. Update #4524.
* score: INTERNAL_ERROR_IDLE_THREAD_CREATE_FAILEDSebastian Huber2022-10-141-3/+9
| | | | | | Add the INTERNAL_ERROR_IDLE_THREAD_CREATE_FAILED fatal error in case the creation of an idle thread fails. This may happen due to a failing create extension provided by the application.
* score: Add CPU_THREAD_LOCAL_STORAGE_VARIANTSebastian Huber2022-10-1438-63/+122
| | | | Update #3835.
* config: Changeable size for IDLE stack allocatorSebastian Huber2022-10-142-12/+11
| | | | | | | | Allow the IDLE stack allocator to change the stack size. This can be used by applications with a very dynamic thread-local storage size to adjust the thread storage area of the IDLE tasks dynamically. Update #4524.
* score: Require power of two CPU_STACK_MINIMUM_SIZESebastian Huber2022-10-144-4/+10
| | | | | For most CPU ports this was already the case. This makes it possible to use the size as an object alignment using RTEMS_ALIGNED().
* bsps/riscv: Add Microchip PolarFire SoC BSP variantPadmarao Begari2022-09-202-2/+2
| | | | | | | | The Microchip PolarFire SoC support is implemented as a riscv BSP variant to boot with any individual hart(cpu core) or SMP based on the boot HARTID configurable and support components are 4 CPU Cores (U54), Interrupt controller (PLIC), Timer (CLINT), UART.
* Do not use RTEMS_INLINE_ROUTINESebastian Huber2022-09-1941-121/+121
| | | | | | | Directly use "static inline" which is available in C99 and later. This brings the RTEMS implementation closer to standard C. Close #3935.
* score: Prevent an out of bounds warningSebastian Huber2022-09-121-2/+7
| | | | Update #4702.
* score: Remove _CPU_Counter_difference()Sebastian Huber2022-09-0920-177/+12
| | | | | | | All CPU ports used the same _CPU_Counter_difference() implementation. Remove this CPU port interface and mandate a monotonically increasing CPU counter. Close #3456.
* powerpc: Add support for VRSAVESebastian Huber2022-09-083-15/+92
| | | | | | | | | | | | | | The VRSAVE feature of the Altivec unit can be used to reduce the amount of Altivec registers which need to be saved/restored during interrupt processing and context switches. In order to use the VRSAVE optimization a corresponding multilib (-mvrsave) is required, see GCC configuration. The -mvrsave option must be added to the ABI_FLAGS of the BSP. Currently only the -mcpu=e6500 based QorIQ BSP support this optimization. Update #4712.
* cpu.h: Fix gcc 12 warningsRyan Long2022-08-191-2/+18
| | | | | | | | Added two pragmas to address, and changed the value of AARCH64_EXCEPTION_MAKE_ENUM_64_BIT to INT_MAX because the old value was not in range of an int. Updates #4662
* cpukit/libdl: Add support for AArch64Ryan Long2022-07-291-0/+256
| | | | | | rtl-mdreloc-aarch64.c and elf_machdep.h came from NetBSD. Updates #4682
* score: Use PTHREAD_CANCELED for _Thread_Cancel()Sebastian Huber2022-07-281-5/+5
| | | | | | | | | | The rtems_task_delete() directive is basically just a combined pthread_cancel() and pthread_join(). In addition, it removes the PTHREAD_DETACHED state. The exit value returned by pthread_join() of threads cancelled by rtems_task_delete() should reflect this by getting a PTHREAD_CANCELED value instead of NULL which could be a normal exit value. Close #4680.
* score: Use priority inheritance for thread joinSebastian Huber2022-07-282-68/+59
| | | | | | | | | | | | | | | | | | | | | Threads may join the thread termination of another thread using the pthread_join() or rtems_task_delete() directives. The thread cancel operation used a special case priority boosting mechanism implemented by _Thread_Raise_real_priority(). The problem was that this approach * is not transitive, * does not account for priority adjustments of the calling task while waiting for the join, * does not support clustered scheduling, and * does not detect deadlocks. All these problems are fixed by using a priority inheritance thread queue for the join operation. Close #4679.
* Use __asm__ for standard C compatibilitySebastian Huber2022-07-271-5/+5
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* score: Remove PRIORITY_PSEUDO_ISR thread prioritySebastian Huber2022-07-2616-69/+43
| | | | | | | | | | | | | | | The uniprocessor schedulers had some special case logic for the PRIORITY_PSEUDO_ISR priority. Tasks with a priority of PRIORITY_PSEUDO_ISR were allowed to preempt a not preemptible task. If other higher priority task are made ready while a PRIORITY_PSEUDO_ISR task preempts a not preemptible task, then the other tasks run before the not preemptible task. This made the RTEMS_NO_PREEMPT mode ineffective. Remove the PRIORITY_PSEUDO_ISR special case logic. This simplifies the uniprocessor schedulers. Move the uniprocessor-specific scheduler support to the new header file <rtems/score/scheduleruniimpl.h>. Close #2365.
* aarch64: Use page table level 0Kinsey Moore2022-07-211-1/+0
| | | | | | | | | This alters the AArch64 page table generation and mapping code and MMU configuration to use page table level 0 in addition to levels 1, 2, and 3. This allows the mapping of up to 48 bits of memory space and is the maximum that can be mapped without relying on additional processor extensions. Mappings are restricted based on the number of physical address bits that the CPU supports.
* score: Fix unlimited objects supportSebastian Huber2022-07-181-5/+7
| | | | | | | | Commit 21275b58a5a69c3c838082ffc8a7a3641f32ea9a ("score: Static Objects_Information initialization") introduced an off-by-one error in the maintenance of inactive objects. Close #4677.
* score: Fix _Objects_Active_count()Sebastian Huber2022-07-181-5/+13
| | | | | | | With unlimited objects the object maximum may be larger than the sum of active and inactive objects. Update #4677.
* score: Extend memory dirty/zero actionsSebastian Huber2022-07-153-2/+61
| | | | | | Dirty or zero also the part of the .noinit section used by RTEMS. Close #4678.
* score: Use RTEMS_SMP in _Thread_Create_idle()Sebastian Huber2022-07-071-1/+5
| | | | | | Conditional expressions with inline functions are not optimized away if optimization is disabled. Avoid such expressions to prevent dead branches.
* score: Conditional _Thread_Priority_replace()Sebastian Huber2022-07-071-0/+2
| | | | This function is only used in SMP configurations.
* cpukit/aarch64: Remove _CPU_ISR_install_vectorKinsey Moore2022-07-052-31/+0
| | | | This function was never actually used and is dead code.
* score: Add _CPU_Use_thread_local_storage()Sebastian Huber2022-07-0420-0/+207
| | | | | | | | | | | | At some point during system initialization, the idle threads are created. Afterwards, the boot processor basically executes within the context of an idle thread with thread dispatching disabled. On some architectures, the thread-local storage area of the associated thread must be set in dedicated processor registers. Add the new CPU port function to do this: void _CPU_Use_thread_local_storage( const Context_Control *context ) Close #4672.
* gcov: Add functions to dump the gcov informationSebastian Huber2022-07-043-0/+243
| | | | Update #4670.
* riscv: Include missing header fileSebastian Huber2022-06-241-0/+2
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* score: Make SMP only code explicitSebastian Huber2022-06-234-3/+31
| | | | | | | Conditional expressions with inline functions are not optimized away if optimization is disabled. Avoid such expressions to prevent dead branches. It helps also during code review to immediately see if a loop is used or not.
* kern_tc.c: Provide a weak hardpps() implementationSebastian Huber2022-06-231-0/+12
| | | | | | | The real implementation of hardpps() is defined in kern_ntptime.c. Use it only if the NTP support is needed by the application. Update #2349.
* score: Use right clock for threadq timeoutsSebastian Huber2022-06-231-2/+2
| | | | | | | | Use CLOCK_REALTIME and CLOCK_MONOTONIC for relative thread queue timeouts instead of CLOCK_REALTIME_COARSE and CLOCK_MONOTONIC_COARSE. This fixes an issue with clock_nanosleep() in combination with clock_gettime(). Close #4669.
* score/cpu: Silence ARM and AARCH64 GCC 12 false trigger array warningChris Johns2022-06-152-1/+7
| | | | | | | | | | | | The false trigger is covered in: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99578 GCC 11 and 12 has been patched for constant pointer casts above 4K. This code casts a constant pointer within the first 4K page. As a result the patch disables the warning. Updates #4662
* kern_tc.c: Update pps_event() for uniprocessor configurationsGabriel Moyano2022-06-101-0/+6
| | | | | | Since pps->capgen equal to zero is not a special value in uniprocessor configurations, there is no need to check for this condition. Update #2349
* arm: Fix PMSA regions for contiguous sectionsSebastian Huber2022-06-081-4/+4
| | | | | | | | | | Sections with identical attributes may be contiguous with a respective begin and end address which is not on a minimum region boundary. The begin address is aligned down to the region base address. The end address is aligned up to the region end address. Account for this in the check for contiguous sections. Update #4202.
* arm: Fix PMSA region mapping with 0x0 end addressSebastian Huber2022-06-081-1/+1
| | | | | | | | A section may span up to the end of the address range. In this case the end address is zero. Use the base address to check if a region should be before another region. Update #4202.
* arm: Fix typoSebastian Huber2022-06-031-2/+2
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* score: Fix pps_fetch()Sebastian Huber2022-05-271-1/+2
| | | | | | Return early only if there was a timeout, otherwise return the PPS info. Update #2349.
* score: Reformat for code coverageSebastian Huber2022-05-231-2/+18
| | | | Close #2349.
* timepps.h: PPS_SYNC defined by defaultGabriel Moyano2022-05-231-10/+0
| | | | Update #2349.
* kern_ntptime.c: Add define in order to remove warningGabriel Moyano2022-05-231-0/+3
| | | | Update #2349.
* kern_tc.c: Enable PPS API supportGabriel Moyano2022-05-231-4/+0
| | | | Update #2349.
* kern_tc.c: Add definitions required by PPS APIGabriel Moyano2022-05-231-0/+6
| | | | Update #2349.
* score: Rename tc_getfrequency()Gabriel Moyano2022-05-231-1/+1
| | | | | | Rename tc_getfrequency() to _Timecounter_Get_frequency(). Update #2349.