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* psxrwlock01: Use an initilized lock for testsHEADmasterSebastian Huber5 hours1-8/+20
| | | | Close #4738.
* config: CONFIGURE_MAXIMUM_THREAD_LOCAL_STORAGE_SIZESebastian Huber27 hours1-47/+48
| | | | | Move CONFIGURE_MAXIMUM_THREAD_LOCAL_STORAGE_SIZE to the general configuration options.
* validation: Fix wordingSebastian Huber27 hours1-6/+6
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* bsp/aarch64: Add new Raspberry Pi 4B BSPMohd Noor Aman2 days11-0/+1132
| | | | | | | | | | | | | | | | | This patch adds new Raspberry pi 4B AArch64 BSP to the RTEMS Family. Currently only LP64 ABI is supported. ILP32 is not supported. RAM starts from 0x80000 in 64Bit kernel mode and MMU from 0x0. All Raspberrypi Pi 4B models and Raspberry Pi 400 are supported. All the IRQs are similiar to the older Raspberry pi 2 ARM BSP. Raspberry Pi 4B has 2 types of UARTs. Only PL011 serial is supported currently. Mini-UART is not supported. Mini-UART is default UART on the board so it needs to be disabled by adding "dtoverlay=disable-bt" to the config.txt. No support for additional 4 PL011-UARTs on the board. The raspberrypi.h includes many of the address required for the future development of the RPi 4B BSP. This includes peripherals, ARM Timer, VideoCore Timer, Watchdog, Mailbox, AUX, FIQs and IRQs.
* rtems: Clarify application config info APISebastian Huber3 days2-221/+625
| | | | Update #3993.
* cpukit/fdt: Free index before containerKinsey Moore4 days1-2/+2
| | | | | | | Ensure that the index is released before the structure containing it is freed and NULLed. Updates #4460
* cpukit/fdt: Check correct allocationKinsey Moore4 days1-1/+1
| | | | | | | | The second allocation check was mistakenly rechecking the first allocation. It now checks the correct allocation and ensures that names is not NULL. Updates #4462
* rtems: Fix formatSebastian Huber7 days1-1/+1
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* validation: Remove unused test suiteSebastian Huber9 days3-115/+0
| | | | Update #3716.
* score: Simplify Chain_Node definitionSebastian Huber2022-09-231-16/+6
| | | | Fix documentation.
* rtems: Add rtems_clock_get_ticks_since_boot() functionSebastian Huber2022-09-233-14/+115
| | | | | This function was declared, however, a definition was missing. Add a validation test for it.
* bsps: Fix format specifierSebastian Huber2022-09-231-1/+1
| | | | Close #4722.
* rtems: Fix typo in rtems_build_name() definitionSebastian Huber2022-09-221-1/+1
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* build: Install SHA header filesSebastian Huber2022-09-221-0/+3
| | | | Update #3719.
* bsps/arm: Mark functions in start.SSebastian Huber2022-09-221-0/+2
| | | | | | | Add the function type to _start() and bsp_start_hook_0_done() so that the linker can generate ARM/Thumb interworking code. Update #4202.
* bsps/arm: Move bsp_start_hook_0_done()Sebastian Huber2022-09-222-2/+6
| | | | Declare bsp_start_hook_0_done() in <bsp/start.h>.
* bsps/arm: Add comment about banked FIQ registersSebastian Huber2022-09-221-0/+1
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* bsps/shared/: Use device tree blobPadmarao Begari2022-09-201-0/+8
| | | | | | If the bsp is integrated and supported a device tree blob(dtb) then use dtb instead of using it from the U-Boot (BSP_START_COPY_FDT_FROM_U_BOOT=False).
* bsps/riscv: Add Microchip PolarFire SoC BSP variantPadmarao Begari2022-09-2022-9/+221
| | | | | | | | The Microchip PolarFire SoC support is implemented as a riscv BSP variant to boot with any individual hart(cpu core) or SMP based on the boot HARTID configurable and support components are 4 CPU Cores (U54), Interrupt controller (PLIC), Timer (CLINT), UART.
* spec/build/bsps: Add dtb supportPadmarao Begari2022-09-202-0/+39
| | | | Add dtb and dtb header path configurable build option
* bsps/riscv: Add device tree blobPadmarao Begari2022-09-202-0/+967
| | | | | | | | | | | | | | | | | Add the basic Microchip PolarFire SoC device tree source and blob The mpfs-dtb.h is generated by the bin2hex https://github.com/padmaraob/bin2hex 1.Compile and build the bin2hex.c $ gcc -o bin2hex bin2hex.c 2.Generate the mpfs.dtb from the mpfs.dts $ dtc -O dtb -o mpfs.dtb mpfs.dts 3.Generate the mpfs-dtb.h Header file from the mpfs.dtb. $ ./bin2hex mpfs.dtb
* bsp/tms570: Fix TMS570_USE_HWINIT_STARTUPSebastian Huber2022-09-203-3/+19
| | | | Make sure only one module is built which defines bsp_start_hook_0().
* bsp/tms570: Fix declarationsSebastian Huber2022-09-201-4/+4
| | | | This avoids multiple definition errors.
* bsp/tms570: Add -mbe32 to LINKFLAGSSebastian Huber2022-09-202-0/+19
| | | | | | | | | | | | | | | | There is not just big-endian on ARM. We have two variants BE32 (obsolete) and BE8. The Cortex-R5F processor supports only BE8, however, some TMS570 variants are BE32 internally. In GCC 8 and later, the --be8 option is passed to the linker based on the selected architecture or CPU. Use BE32 by default for the TMS570 BSP. In GCC, see: commit 63d03dcecdafe34715282a5155cfc2162375feca Author: Richard Earnshaw <rearnsha@arm.com> Date: Mon Jul 3 13:22:05 2017 +0000 [arm] Clean up generation of BE8 format images.
* bsps/riscv/riscv: Fix fe310_uart_readAlan Cudmore2022-09-191-2/+5
| | | | | | | | | | | Note: Resending after learning how to use git send-email, please disregard previous message. This fixes the riscv fe310 console driver fe310_uart_read function. The function reads the RX status/data register to check if data is available, but discards the data and reads it a seconds time. Also cleared the interrupt enable bit in the first_open function. Close #4719
* Do not use RTEMS_INLINE_ROUTINESebastian Huber2022-09-19150-1039/+1039
| | | | | | | Directly use "static inline" which is available in C99 and later. This brings the RTEMS implementation closer to standard C. Close #3935.
* validation: Test deadlock detection special caseSebastian Huber2022-09-122-0/+191
| | | | Update #3716.
* score: Prevent an out of bounds warningSebastian Huber2022-09-121-2/+7
| | | | Update #4702.
* validation: Fix integer type warningSebastian Huber2022-09-091-1/+1
| | | | Update #4662.
* score: Remove _CPU_Counter_difference()Sebastian Huber2022-09-0923-187/+19
| | | | | | | All CPU ports used the same _CPU_Counter_difference() implementation. Remove this CPU port interface and mandate a monotonically increasing CPU counter. Close #3456.
* libcrypt: There is no need to clear message digestXin LI2022-09-082-4/+0
| | | | | | | | context after they are finialized after r336539, so do not do it. Submitted by: David CARLIER <devnexen gmail com> MFC after: 1 month (after r336539) Differential Revision: https://reviews.freebsd.org/D16059
* Get rid of unused variables.Xin LI2022-09-082-16/+2
| | | | | | | | | copied_key and copied_salt are assigned with NULL and never used otherwise. Remove the two variables and related code. Reviewed by: pfg MFC after: 2 weeks Differential Revision: https://reviews.freebsd.org/D16314
* lib: further adoption of SPDX licensing ID tags.Pedro F. Giffuni2022-09-083-2/+8
| | | | | | | | | | | | Mainly focus on files that use BSD 2-Clause license, however the tool I was using mis-identified many licenses so this was mostly a manual - error prone - task. The Software Package Data Exchange (SPDX) group provides a specification to make it easier for automated tools to detect and summarize well known opensource licenses. We are gradually adopting the specification, noting that the tags are considered only advisory and do not, in any way, superceed or replace the license texts.
* General further adoption of SPDX licensing ID tags.Pedro F. Giffuni2022-09-081-1/+3
| | | | | | | | | | | | | | Mainly focus on files that use BSD 3-Clause license. The Software Package Data Exchange (SPDX) group provides a specification to make it easier for automated tools to detect and summarize well known opensource licenses. We are gradually adopting the specification, noting that the tags are considered only advisory and do not, in any way, superceed or replace the license texts. Special thanks to Wind River for providing access to "The Duke of Highlander" tool: an older (2014) run over FreeBSD tree was useful as a starting point.
* libtests/sha: Add tests for SHA512-256Sebastian Huber2022-09-081-0/+49
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* libtests/sha: Add tests for SHA512-224Sebastian Huber2022-09-081-0/+50
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* libtests/sha: Add tests for SHA384Sebastian Huber2022-09-081-0/+58
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* libtests/sha: Add tests for SHA224Sebastian Huber2022-09-081-4/+54
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* libmd: Always erase context in _Final method,Xin LI2022-09-082-5/+5
| | | | | | | | | | and when doing it, consistently use explicit_bzero(). Update manual pages to match the behavior. Reviewed by: pfg, allanjude, jmg MFC after: 1 month Differential Revision: https://reviews.freebsd.org/D16316
* Implement SHA2-224 submode of SHA2-256Conrad Meyer2022-09-082-0/+113
| | | | | Like SHA2-384:SHA2-512, SHA2-224 is simply a truncated SHA2-256 with a different initial vector. Add to round out the complete basic SHA2 family.
* Fix C++ includability of crypto headers with static array sizesAlan Somers2022-09-084-5/+10
| | | | | | | | | | | | | | | | | C99 allows array function parameters to use the static keyword for their sizes. This tells the compiler that the parameter will have at least the specified size, and calling code will fail to compile if that guarantee is not met. However, this syntax is not legal in C++. This commit reverts r300824, which worked around the problem for sys/sys/md5.h only, and introduces a new macro: min_size(). min_size(x) can be used in headers as a static array size, but will still compile in C++ mode. Reviewed by: cem, ed MFC after: 4 weeks Sponsored by: Spectra Logic Corp Differential Revision: https://reviews.freebsd.org/D8277
* Retune SHA2 code for improved performance on CPUsColin Percival2022-09-082-190/+198
| | | | | | | | | | | | | | | with more ILP and a preference for memory load instructions over large code footprints with embedded immediate variables. On amd64 CPUs from 2007-2008 there is not a significant change, but amd64 CPUs from 2009-2010 get roughly 10% more throughput with this code; amd64 CPUs from 2011-2012 get roughly 15% more throughput; and AMD64 CPUs from 2013-2015 get 20-25% more throughput. The Raspberry Pi 2 increases its throughput by 6-8%. Sponsored by: Tarsnap Backup Inc. Performance tested by: allanjude MFC after: 3 weeks
* Implement SHA-512 truncated (224 and 256 bits)Allan Jude2022-09-082-0/+150
| | | | | | | | | | | | | | | | | | | This implements SHA-512/256, which generates a 256 bit hash by calculating the SHA-512 then truncating the result. A different initial value is used, making the result different from the first 256 bits of the SHA-512 of the same input. SHA-512 is ~50% faster than SHA-256 on 64bit platforms, so the result is a faster 256 bit hash. The main goal of this implementation is to enable support for this faster hashing algorithm in ZFS. The feature was introduced into ZFS in r289422, but is disconnected because SHA-512/256 support was missing. A further commit will enable it in ZFS. This is the follow on to r292782 Reviewed by: cem Sponsored by: ScaleEngine Inc. Differential Revision: https://reviews.freebsd.org/D6061
* crypto routines: Hint minimum buffer sizes to the compilerConrad Meyer2022-09-085-9/+10
| | | | | | | | | | | Use the C99 'static' keyword to hint to the compiler IVs and output digest sizes. The keyword informs the compiler of the minimum valid size for a given array. Obviously not every pointer can be validated (i.e., the compiler can produce false negative but not false positive reports). No functional change. No ABI change. Sponsored by: EMC / Isilon Storage Division
* Replace sys/crypto/sha2/sha2.c with lib/libmd/sha512c.cAllan Jude2022-09-084-19/+149
| | | | | | | | | | | | | | | | | | cperciva's libmd implementation is 5-30% faster The same was done for SHA256 previously in r263218 cperciva's implementation was lacking SHA-384 which I implemented, validated against OpenSSL and the NIST documentation Extend sbin/md5 to create sha384(1) Chase dependancies on sys/crypto/sha2/sha2.{c,h} and replace them with sha512{c.c,.h} Reviewed by: cperciva, des, delphij Approved by: secteam, bapt (mentor) MFC after: 2 weeks Sponsored by: ScaleEngine Inc. Differential Revision: https://reviews.freebsd.org/D3929
* minimum: Do not use unified work areasSebastian Huber2022-09-081-15/+0
| | | | | | | The CONFIGURE_UNIFIED_WORK_AREAS option pulls in a system initialization handler which initializes the unified heap. Close #4108.
* bsp/qoriq: Enable VRSAVE optimizationSebastian Huber2022-09-081-0/+2
| | | | Close #4712.
* powerpc: Add support for VRSAVESebastian Huber2022-09-085-23/+429
| | | | | | | | | | | | | | The VRSAVE feature of the Altivec unit can be used to reduce the amount of Altivec registers which need to be saved/restored during interrupt processing and context switches. In order to use the VRSAVE optimization a corresponding multilib (-mvrsave) is required, see GCC configuration. The -mvrsave option must be added to the ABI_FLAGS of the BSP. Currently only the -mcpu=e6500 based QorIQ BSP support this optimization. Update #4712.
* rtems: Include <rtems/score/cpuopts.h>Sebastian Huber2022-09-083-0/+3
| | | | | Directly include <rtems/score/cpuopts.h> in header files using CPU build options.
* score: Improve formattingSebastian Huber2022-09-081-4/+10
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