riscv: Rework CPU counter support

Update #3433.

4 files changed, 91 insertions, 5 deletions

diff --git a/cpukit/score/cpu/riscv/Makefile.am b/cpukit/score/cpu/riscv/Makefile.am
index 40fcd1ff75..bf1c43f01d 100644
--- a/cpukit/score/cpu/riscv/Makefile.am
+++ b/cpukit/score/cpu/riscv/Makefile.am
@@ -8,6 +8,7 @@ libscorecpu_a_SOURCES += riscv-context-switch.S
 libscorecpu_a_SOURCES += riscv-context-initialize.c
 libscorecpu_a_SOURCES += riscv-context-validate.S
 libscorecpu_a_SOURCES += riscv-context-volatile-clobber.S
+libscorecpu_a_SOURCES += riscv-counter.S
 
 include $(top_srcdir)/automake/local.am
 include $(srcdir)/headers.am
diff --git a/cpukit/score/cpu/riscv/include/rtems/score/cpu.h b/cpukit/score/cpu/riscv/include/rtems/score/cpu.h
index 039595dd4b..ce73651d97 100644
--- a/cpukit/score/cpu/riscv/include/rtems/score/cpu.h
+++ b/cpukit/score/cpu/riscv/include/rtems/score/cpu.h
@@ -435,13 +435,11 @@ typedef uint32_t CPU_Counter_ticks;
 
 uint32_t _CPU_Counter_frequency( void );
 
+extern volatile uint32_t * const _RISCV_Counter;
+
 static inline CPU_Counter_ticks _CPU_Counter_read( void )
 {
-  unsigned long ticks;
-
-  __asm__ volatile ( "rdtime %0" : "=&r" ( ticks ) );
-
-  return (uint32_t) ticks;
+  return *_RISCV_Counter;
 }
 
 static inline CPU_Counter_ticks _CPU_Counter_difference(
diff --git a/cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h b/cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h
index 4a5f81f617..5a256e8b75 100644
--- a/cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h
+++ b/cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h
@@ -345,6 +345,44 @@ static inline uint32_t _RISCV_Read_FCSR( void )
   return fcsr;
 }
 
+/*
+ * The RISC-V ISA provides a rdtime instruction, however, it is implemented in
+ * most chips via a trap-and-emulate.  Using this in machine mode makes no
+ * sense.  Use the memory-mapped mtime register directly instead.  The address
+ * of this register is platform-specific and provided via the device tree.
+ *
+ * To allow better code generation provide a const (_RISCV_Counter) and a
+ * mutable (_RISCV_Counter_mutable) declaration for this pointer variable
+ * (defined in assembler code).
+ *
+ * See code generated for this test case:
+ *
+ * extern volatile int * const c;
+ *
+ * extern volatile int *v;
+ *
+ * int fc(void)
+ * {
+ *   int a = *c;
+ *   __asm__ volatile("" ::: "memory");
+ *   return *c - a;
+ * }
+ *
+ * int fv(void)
+ * {
+ *   int a = *v;
+ *   __asm__ volatile("" ::: "memory");
+ *   return *v - a;
+ * }
+ */
+extern volatile uint32_t *_RISCV_Counter_mutable;
+
+/*
+ * Initial value of _RISCV_Counter and _RISCV_Counter_mutable.  Must be
+ * provided by the BSP.
+ */
+extern volatile uint32_t _RISCV_Counter_register;
+
 #ifdef RTEMS_SMP
 
 static inline struct Per_CPU_Control *_RISCV_Get_current_per_CPU_control( void )
diff --git a/cpukit/score/cpu/riscv/riscv-counter.S b/cpukit/score/cpu/riscv/riscv-counter.S
new file mode 100644
index 0000000000..e779325b4b
--- /dev/null
+++ b/cpukit/score/cpu/riscv/riscv-counter.S
@@ -0,0 +1,49 @@
+/*
+ * Copyright (c) 2018 embedded brains GmbH
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#if __riscv_xlen == 32
+#define PTR_ALIGN 2
+#define PTR_SIZE 4
+#define PTR_VALUE .word
+#elif __riscv_xlen == 64
+#define PTR_ALIGN 3
+#define PTR_SIZE 8
+#define PTR_VALUE .dword
+#endif
+
+	.section	.sdata, "aw"
+	.align	PTR_ALIGN
+
+	.globl	_RISCV_Counter
+	.type	_RISCV_Counter, @object
+	.size	_RISCV_Counter, PTR_SIZE
+_RISCV_Counter:
+
+	.globl	_RISCV_Counter_mutable
+	.type	_RISCV_Counter_mutable, @object
+	.size	_RISCV_Counter_mutable, PTR_SIZE
+_RISCV_Counter_mutable:
+
+	PTR_VALUE	_RISCV_Counter_register