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path: root/bsps/riscv/riscv/clock/clockdrv.c (follow)
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* bsps: Avoid unused argument in clock interruptSebastian Huber2024-03-201-8/+5
| | | | | | | | | | | Pass the parameter of the clock interrupt handler to Clock_driver_support_at_tick() and Clock_driver_timecounter_tick(). This makes it possible to use the interrupt handler argument in clock drivers. Use the interrupt handler provided by Clock_driver_support_install_isr() to avoid local delarations of Clock_isr(). Update #4862.
* Update company nameSebastian Huber2023-05-201-1/+1
| | | | | The embedded brains GmbH & Co. KG is the legal successor of embedded brains GmbH.
* bsps/riscv: Use per-CPU mtimecmp in clock driverSebastian Huber2023-03-171-26/+15
| | | | | Use the mtimecmp from the PLIC/CLINT initialization in the clock driver. This register is defined by the device tree and does not assume a fixed mapping.
* clockdrv: Add clock driver implementation groupSebastian Huber2023-01-241-2/+3
| | | | | | Use standard wording in Clock Driver related files. Update #3706.
* bsps/riscv: Add Microchip PolarFire SoC BSP variantPadmarao Begari2022-09-201-1/+5
| | | | | | | | The Microchip PolarFire SoC support is implemented as a riscv BSP variant to boot with any individual hart(cpu core) or SMP based on the boot HARTID configurable and support components are 4 CPU Cores (U54), Interrupt controller (PLIC), Timer (CLINT), UART.
* bsps/riscv: Add missing includeSebastian Huber2022-02-251-0/+1
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* bsps/riscv: Add per cpu clock interruptJan Sommer2021-03-231-10/+49
| | | | - Fixes failure of test smpclock01
* riscv: add freedom E310 Arty A7 bspPragnesh Patel2019-10-231-5/+11
| | | | | | | Added support for Sifive Freedom FE310 soc on Arty A7 FPGA board. Update #3785. Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
* riscv: add griscv bspJiri Gaisler2019-01-221-0/+5
| | | | Update #3678.
* bsp/riscv: Fix clock driverSebastian Huber2018-08-011-17/+49
| | | | | | Do not assume that mtime is zero at boot time. Update #3433.
* riscv: Rework CPU counter supportSebastian Huber2018-07-271-4/+18
| | | | Update #3433.
* bsp/riscv: Add simple SMP support to clock driverSebastian Huber2018-07-251-0/+2
| | | | | | This is a hack. The clock interrupt should be handled by each hart. Update #3433.
* bsp/riscv: Add basic SMP startupSebastian Huber2018-07-251-8/+2
| | | | Update #3433.
* riscv: Add CLINT and PLIC supportSebastian Huber2018-07-251-5/+4
| | | | | | The CLINT and PLIC need some per-processor state. Update #3433.
* bsp/riscv: Add and use riscv_fdt_get_address()Sebastian Huber2018-07-251-15/+31
| | | | Update #3433.
* riscv: Rework exception handlingSebastian Huber2018-07-251-5/+14
| | | | | | | | | | | Remove _CPU_ISR_install_raw_handler() and _CPU_ISR_install_vector() functions. Applications can install an exception handler via the fatal error handler to handle synchronous exceptions. Handle interrupt exceptions via _RISCV_Interrupt_dispatch() which must be provided by the BSP. Update #3433.
* riscv: Implement CPU counterSebastian Huber2018-07-061-10/+2
| | | | Update #3433.
* riscv: Avoid namespace pollutionSebastian Huber2018-06-281-0/+1
| | | | | | | Remove <rtems/score/riscv-utility.h> include from <rtems/score/cpu.h> (which is visible via <rtems.h> for example). Update #3433.
* bsp/riscv: Rework clock driverSebastian Huber2018-06-281-41/+67
| | | | | | | Use device tree provided timebase frequency. Do not write to read-only mtime register. Update #3433.
* bsp/riscv_generic: Rename to "riscv"Sebastian Huber2018-06-271-0/+122
Update #3433.
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