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* bsps: Move declarations to <bsp/irq-generic.h>Sebastian Huber2024-03-272-14/+0
| | | | | | | | | | | Move declarations of bsp_interrupt_get_affinity() and bsp_interrupt_set_affinity() to <bsp/irq-generic.h>. Canonicalize the <bsp/irq.h> includes. Implement bsp_interrupt_get_affinity() and bsp_interrupt_set_affinity() only if needed (usually RTEMS_SMP). Provide stub implementations for i386 to fix build errors.
* bsps: Avoid unused argument in clock interruptSebastian Huber2024-03-201-8/+5
| | | | | | | | | | | Pass the parameter of the clock interrupt handler to Clock_driver_support_at_tick() and Clock_driver_timecounter_tick(). This makes it possible to use the interrupt handler argument in clock drivers. Use the interrupt handler provided by Clock_driver_support_install_isr() to avoid local delarations of Clock_isr(). Update #4862.
* Update company nameSebastian Huber2023-05-2010-10/+10
| | | | | The embedded brains GmbH & Co. KG is the legal successor of embedded brains GmbH.
* bsps/riscv: add riscv/kendrytek210 BSP variant source changesAlan Cudmore2023-03-287-6/+171
| | | | | | | | | This patch adds support for the Kendryte K210 RISC-V BSP variant. The SoC uses the existing Interrupt Controller, Timer, and console UART. It only needs SoC specific initialization and an embedded device tree binary similar to the polarfire SoC BSP. Updates #4876
* bsps/riscv: add device tree source and device tree blob header for k210 bsp ↵Alan Cudmore2023-03-282-0/+531
| | | | | | | | | | variant This patch adds the k210 device tree source and the corresponding device tree blob encoded in the header which is used for the embedded device tree blob for the Kendryte K210 BSP variant. Updates #4876
* bsps/riscv: Use per-CPU mtimecmp in clock driverSebastian Huber2023-03-171-26/+15
| | | | | Use the mtimecmp from the PLIC/CLINT initialization in the clock driver. This register is defined by the device tree and does not assume a fixed mapping.
* bsps/riscv: Fix riscv_get_hart_index_by_phandle()Sebastian Huber2023-03-172-2/+10
| | | | Take a non-zero RISCV_BOOT_HARTID into account.
* bsps/riscv: Make SMP start more robustSebastian Huber2023-03-171-4/+1
| | | | | | | In SMP configurations, check that we run on a configured processor. If not, then there is not much that can be done since we do not have a stack available for this processor. Just loop forever in this case. Do this in assemlby to ensure that no stack memory is used.
* clockdrv: Add clock driver implementation groupSebastian Huber2023-01-241-2/+3
| | | | | | Use standard wording in Clock Driver related files. Update #3706.
* tm27: Avoid function pointer castsSebastian Huber2023-01-241-4/+2
| | | | | | | Add TM27_USE_VECTOR_HANDLER to select the interrupt handler type used by the <tm27.h> implementation. Close #4820.
* riscv: Resurrect RISCV_ENABLE_HTIF_SUPPORTSebastian Huber2023-01-125-10/+30
| | | | | | | | Low-end configurations may want to have the HTIF support removed. Enable the option by default. Fix formatting. Fix node validity checks. Updates #4779.
* RISC-V: Always probe for HTIF and remove RISCV_ENABLE_HTIF_SUPPORTHesham Almatary2022-12-235-24/+18
| | | | Updates #4779
* bsps/irq: Rename handler in dispatch tableSebastian Huber2022-12-021-2/+2
| | | | | | | The name handler table was a bit misleading after the last rework. Rename it to distach table. Update the documentation accordingly. Update #4769.
* bsps/riscv: Simplify PLIC supportSebastian Huber2022-11-231-28/+30
| | | | | In uniprocessor configurations there is no need to take interrupt affinities into account for the interrupt vector enable/disable.
* bsps/riscv: Fix PLIC enable register countSebastian Huber2022-11-231-3/+5
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* bsps/riscv: Add riscv_plic_cpu_0_init()Sebastian Huber2022-11-231-13/+23
| | | | Move boot processor initialization of PLIC to separate function.
* bsps/riscv: Fix bsp_fdt_map_intr()Sebastian Huber2022-11-231-1/+1
| | | | | The interrupt numbers in the device tree are usually PLIC interrupts. Map the number to the vector number associated with an external interrupt.
* bsps/riscv: Fix software interrupt dispatchingSebastian Huber2022-11-111-2/+4
| | | | | | | In SMP configurations, there may be no software interrupt handler installed when the software interrupt is processed. Add the new interrupt handler dispatch variant bsp_interrupt_handler_dispatch_unlikely() for this special case.
* bsps/riscv: Fix PLIC enable register countSebastian Huber2022-11-101-2/+2
| | | | Each PLIC enable register has 32 bits, so we have to divide by 32.
* bsps/riscv: Skip init on not configured processorsSebastian Huber2022-11-101-0/+11
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* bsps/riscv: Simplify riscv_plic_init()Sebastian Huber2022-11-101-30/+39
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* bsps/riscv: Simplify riscv_clint_init()Sebastian Huber2022-11-101-14/+25
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* bsps/riscv: Add tm27 supportSebastian Huber2022-11-101-1/+136
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* bsps/riscv: Always dispatch software interruptsSebastian Huber2022-11-101-3/+2
| | | | This helps to run the interrupt API validation tests.
* bsps/riscv: bsp_interrupt_get/set_affinity()Sebastian Huber2022-11-101-13/+6
| | | | | Provide bsp_interrupt_get_affinity() and bsp_interrupt_set_affinity() only if RTEMS_SMP is enabled. Replace fatal error with a status code.
* bsps/riscv: bsp_interrupt_raise_on()Sebastian Huber2022-11-101-4/+20
| | | | Implement bsp_interrupt_raise_on() and bsp_interrupt_raise().
* bsps/riscv: bsp_interrupt_is_pending()Sebastian Huber2022-11-101-2/+25
| | | | Implement this function.
* bsps/riscv: bsp_interrupt_get_attributes()Sebastian Huber2022-11-101-0/+15
| | | | Implement this function.
* bsps/riscv: Improve bsp_interrupt_vector_disable()Sebastian Huber2022-11-101-0/+8
| | | | Add support for hart-specific software and timer interrupts.
* bsps/riscv: Improve bsp_interrupt_vector_enable()Sebastian Huber2022-11-101-0/+8
| | | | Add support for hart-specific software and timer interrupts.
* bsps/riscv: bsp_interrupt_vector_is_enabled()Sebastian Huber2022-11-101-2/+47
| | | | Implement this function.
* bsps/riscv: bsp_interrupt_is_valid_vector()Sebastian Huber2022-11-102-1/+18
| | | | Implement this function.
* bsps: Improve riscv console FDT parsingAlan Cudmore2022-10-141-9/+5
| | | | | | | | | | This fixes a problem with parsing the FDT compatible property by replacing the RISCV_CONSOLE_IS_COMPATIBLE macro with calls to the fdt_stringlist_contains function. The macro only works when the compatible FDT entry is a single string and not a list of strings. The new call will compare each item in the string list. Close #4728.
* riscv: Move functions to avoid build issuesSebastian Huber2022-10-141-10/+0
| | | | | The _RISCV_Map_cpu_index_to_hardid() and _RISCV_Map_hardid_to_cpu_index() functions must be available to all riscv BSPs.
* bsps/riscv: Add Microchip PolarFire SoC BSP variantPadmarao Begari2022-09-207-4/+130
| | | | | | | | The Microchip PolarFire SoC support is implemented as a riscv BSP variant to boot with any individual hart(cpu core) or SMP based on the boot HARTID configurable and support components are 4 CPU Cores (U54), Interrupt controller (PLIC), Timer (CLINT), UART.
* bsps/riscv: Add device tree blobPadmarao Begari2022-09-202-0/+967
| | | | | | | | | | | | | | | | | Add the basic Microchip PolarFire SoC device tree source and blob The mpfs-dtb.h is generated by the bin2hex https://github.com/padmaraob/bin2hex 1.Compile and build the bin2hex.c $ gcc -o bin2hex bin2hex.c 2.Generate the mpfs.dtb from the mpfs.dts $ dtc -O dtb -o mpfs.dtb mpfs.dts 3.Generate the mpfs-dtb.h Header file from the mpfs.dtb. $ ./bin2hex mpfs.dtb
* bsps/riscv/riscv: Fix fe310_uart_readAlan Cudmore2022-09-191-2/+5
| | | | | | | | | | | Note: Resending after learning how to use git send-email, please disregard previous message. This fixes the riscv fe310 console driver fe310_uart_read function. The function reads the RX status/data register to check if data is available, but discards the data and reads it a seconds time. Also cleared the interrupt enable bit in the first_open function. Close #4719
* bsp/riscv: Add NOEL-V BSPMartin Aberg2022-09-062-0/+4
| | | | | | | | | | | | | | | | | | | | Added support for Cobham Gaisler NOEL-V systems. The NOEL-V support is implemented as a riscv BSP. Both 32-bit and 64-bit processor systems are supported. Cobham Gaisler's NOEL-V RISC-V processor IP is described here: https://www.gaisler.com/NOELV Compatible with the following NOEL-V FPGA example design ranges available from Cobham Gaisler. Follow the links for free bit-streams, DTS/DTB, user's manuals and quick-start guides: - NOEL-ARTYA7-EX (https://www.gaisler.com/NOEL-ARTYA7) - NOEL-PF-EX (https://www.gaisler.com/NOEL-PF) - NOEL-XCKU-EX (https://www.gaisler.com/NOEL-XCKU) Uses the shared GRLIB APBUART console driver "apbuart_termios.c". APBUART devices are probed using device tree. Closes #4225.
* bsps/riscv: Add missing includeSebastian Huber2022-02-251-0/+1
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* bsp_specs: Delete last remnants of these.Joel Sherrill2021-11-291-0/+0
| | | | Updates #3937.
* build: Remove old build systemSebastian Huber2021-09-212-62/+0
| | | | | Close #3250. Close #4081.
* score: Canonicalize _CPU_Fatal_halt()Sebastian Huber2021-07-281-1/+2
| | | | | | | | Move _CPU_Fatal_halt() declaration to <rtems/score/cpuimpl.h> and make sure it is a proper declaration of a function which does not return. Fix the type of the error code. If necessary, add the implementation to cpu.c. Implementing _CPU_Fatal_halt() as a function makes it possible to wrap this function for example to fully test _Terminate().
* bsps/irq: bsp_interrupt_facility_initialize()Sebastian Huber2021-07-271-3/+1
| | | | | | Do not return a status code in bsp_interrupt_facility_initialize() since this leads to unreachable code in bsp_interrupt_initialize(). Use RTEMS_DEBUG assertions in bsp_interrupt_facility_initialize() if necessary.
* bsps/irq: bsp_interrupt_set_affinity()Sebastian Huber2021-07-262-4/+6
| | | | | | Return a status code for bsp_interrupt_set_affinity(). Update #3269.
* bsps/irq: bsp_interrupt_get_affinity()Sebastian Huber2021-07-262-2/+4
| | | | | | Return a status code for bsp_interrupt_get_affinity(). Update #3269.
* bsps/irq: bsp_interrupt_vector_disable()Sebastian Huber2021-07-261-1/+3
| | | | | | Return a status code for bsp_interrupt_vector_disable(). Update #3269.
* bsps/irq: bsp_interrupt_vector_enable()Sebastian Huber2021-07-261-1/+3
| | | | | | Return a status code for bsp_interrupt_vector_enable(). Update #3269.
* bsps/irq: Add rtems_interrupt_is_pending()Sebastian Huber2021-07-261-0/+11
| | | | | | Add a default implementation which just returns RTEMS_UNSATISFIED. Update #3269.
* bsps/irq: Add rtems_interrupt_get_attributes()Sebastian Huber2021-07-261-0/+8
| | | | | | | Add a default implementation which clears the attributes to zero and just returns RTEMS_SUCCESSFUL for valid parameters. Update #3269.
* bsps/irq: Add rtems_interrupt_raise()Sebastian Huber2021-07-261-0/+23
| | | | | | | | | Add rtems_interrupt_raise_on() and rtems_interrupt_clear(). Add a default implementation which just returns RTEMS_UNSATISFIED for valid parameters. Update #3269.
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