| Commit message (Collapse) | Author | Age | Files | Lines |
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Pass the parameter of the clock interrupt handler to
Clock_driver_support_at_tick() and Clock_driver_timecounter_tick(). This makes
it possible to use the interrupt handler argument in clock drivers.
Use the interrupt handler provided by Clock_driver_support_install_isr() to
avoid local delarations of Clock_isr().
Update #4862.
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The embedded brains GmbH & Co. KG is the legal successor of embedded
brains GmbH.
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Use the mtimecmp from the PLIC/CLINT initialization in the clock driver. This
register is defined by the device tree and does not assume a fixed mapping.
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Use standard wording in Clock Driver related files.
Update #3706.
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The Microchip PolarFire SoC support is implemented as a
riscv BSP variant to boot with any individual hart(cpu core)
or SMP based on the boot HARTID configurable and support
components are 4 CPU Cores (U54), Interrupt controller (PLIC),
Timer (CLINT), UART.
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- Fixes failure of test smpclock01
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Added support for Sifive Freedom FE310 soc on Arty A7 FPGA board.
Update #3785.
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
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Update #3678.
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Do not assume that mtime is zero at boot time.
Update #3433.
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Update #3433.
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This is a hack. The clock interrupt should be handled by each hart.
Update #3433.
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Update #3433.
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The CLINT and PLIC need some per-processor state.
Update #3433.
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Update #3433.
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Remove _CPU_ISR_install_raw_handler() and _CPU_ISR_install_vector()
functions. Applications can install an exception handler via the fatal
error handler to handle synchronous exceptions.
Handle interrupt exceptions via _RISCV_Interrupt_dispatch() which must
be provided by the BSP.
Update #3433.
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Update #3433.
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Remove <rtems/score/riscv-utility.h> include from <rtems/score/cpu.h>
(which is visible via <rtems.h> for example).
Update #3433.
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Use device tree provided timebase frequency. Do not write to read-only
mtime register.
Update #3433.
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Update #3433.
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