diff options
| author | Padmarao Begari <padmarao.begari@microchip.com> | 2022-09-19 18:30:26 +0530 |
|---|---|---|
| committer | Joel Sherrill <joel@rtems.org> | 2022-09-20 12:00:51 -0500 |
| commit | 6b0d3c987349d188b65e9fc8229daeba247928c5 (patch) | |
| tree | 4f6f37aaab9be619b82612eb4f000a42549488ca /bsps/riscv/riscv/clock/clockdrv.c | |
| parent | spec/build/bsps: Add dtb support (diff) | |
| download | rtems-6b0d3c987349d188b65e9fc8229daeba247928c5.tar.bz2 | |
bsps/riscv: Add Microchip PolarFire SoC BSP variant
The Microchip PolarFire SoC support is implemented as a
riscv BSP variant to boot with any individual hart(cpu core)
or SMP based on the boot HARTID configurable and support
components are 4 CPU Cores (U54), Interrupt controller (PLIC),
Timer (CLINT), UART.
Diffstat (limited to 'bsps/riscv/riscv/clock/clockdrv.c')
| -rw-r--r-- | bsps/riscv/riscv/clock/clockdrv.c | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/bsps/riscv/riscv/clock/clockdrv.c b/bsps/riscv/riscv/clock/clockdrv.c index 65bc7c80ef..d183e65b94 100644 --- a/bsps/riscv/riscv/clock/clockdrv.c +++ b/bsps/riscv/riscv/clock/clockdrv.c @@ -95,6 +95,8 @@ static void riscv_clock_at_tick(riscv_timecounter *tc) uint64_t value; uint32_t cpu = rtems_scheduler_get_processor(); + cpu = _RISCV_Map_cpu_index_to_hardid(cpu); + clint = tc->clint; value = clint->mtimecmp[cpu].val_64; @@ -172,6 +174,8 @@ static void riscv_clock_secondary_action(void *arg) uint64_t *cmpval = arg; uint32_t cpu = _CPU_SMP_Get_current_processor(); + cpu = _RISCV_Map_cpu_index_to_hardid(cpu); + riscv_clock_clint_init(clint, *cmpval, cpu); } #endif @@ -214,7 +218,7 @@ static void riscv_clock_initialize(void) cmpval = riscv_clock_read_mtime(&clint->mtime); cmpval += interval; - riscv_clock_clint_init(clint, cmpval, 0); + riscv_clock_clint_init(clint, cmpval, RISCV_BOOT_HARTID); riscv_clock_secondary_initialization(clint, cmpval, interval); /* Initialize timecounter */ |