Commit message (Expand) | Author | Age | Files | Lines | |
---|---|---|---|---|---|
* | bsps: Avoid unused argument in clock interrupt | Sebastian Huber | 2024-03-20 | 1 | -8/+5 |
* | Update company name | Sebastian Huber | 2023-05-20 | 1 | -1/+1 |
* | bsps/riscv: Use per-CPU mtimecmp in clock driver | Sebastian Huber | 2023-03-17 | 1 | -26/+15 |
* | clockdrv: Add clock driver implementation group | Sebastian Huber | 2023-01-24 | 1 | -2/+3 |
* | bsps/riscv: Add Microchip PolarFire SoC BSP variant | Padmarao Begari | 2022-09-20 | 1 | -1/+5 |
* | bsps/riscv: Add missing include | Sebastian Huber | 2022-02-25 | 1 | -0/+1 |
* | bsps/riscv: Add per cpu clock interrupt | Jan Sommer | 2021-03-23 | 1 | -10/+49 |
* | riscv: add freedom E310 Arty A7 bsp | Pragnesh Patel | 2019-10-23 | 1 | -5/+11 |
* | riscv: add griscv bsp | Jiri Gaisler | 2019-01-22 | 1 | -0/+5 |
* | bsp/riscv: Fix clock driver | Sebastian Huber | 2018-08-01 | 1 | -17/+49 |
* | riscv: Rework CPU counter support | Sebastian Huber | 2018-07-27 | 1 | -4/+18 |
* | bsp/riscv: Add simple SMP support to clock driver | Sebastian Huber | 2018-07-25 | 1 | -0/+2 |
* | bsp/riscv: Add basic SMP startup | Sebastian Huber | 2018-07-25 | 1 | -8/+2 |
* | riscv: Add CLINT and PLIC support | Sebastian Huber | 2018-07-25 | 1 | -5/+4 |
* | bsp/riscv: Add and use riscv_fdt_get_address() | Sebastian Huber | 2018-07-25 | 1 | -15/+31 |
* | riscv: Rework exception handling | Sebastian Huber | 2018-07-25 | 1 | -5/+14 |
* | riscv: Implement CPU counter | Sebastian Huber | 2018-07-06 | 1 | -10/+2 |
* | riscv: Avoid namespace pollution | Sebastian Huber | 2018-06-28 | 1 | -0/+1 |
* | bsp/riscv: Rework clock driver | Sebastian Huber | 2018-06-28 | 1 | -41/+67 |
* | bsp/riscv_generic: Rename to "riscv" | Sebastian Huber | 2018-06-27 | 1 | -0/+122 |