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* bsps/arm: Fix SMP startSebastian Huber2021-07-091-0/+6
| | | | | | | | Skip the data cache initialization if we are a secondary processor. The bug was introduced by e164df5e33608576443b4cd5923a9046358ee773 and did not show up in tests using Qemu since the data cache behaviour is not emulated.
* bsps/arm: Add start up support for ARMv6 RPi ModelsPranav Dangi2021-07-071-1/+7
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* bsps/irq: Use BSP_INTERRUPT_VECTOR_COUNTSebastian Huber2021-06-242-2/+2
| | | | | | Use BSP_INTERRUPT_VECTOR_COUNT instead of BSP_INTERRUPT_VECTOR_MAX. Update #3269.
* bsps/irq: Remove BSP_INTERRUPT_VECTOR_MINSebastian Huber2021-06-241-1/+1
| | | | | | | | | | Remove BSP_INTERRUPT_VECTOR_MIN and unconditionally let interrupt vector numbers start with zero. The BSP_INTERRUPT_VECTOR_MIN == 0 invariant was tested by the previous commit and building all BSPs. Update #3269.
* bsps: Support RTEMS_NOINIT in linkcmdsSebastian Huber2021-05-021-0/+7
| | | | Update #3866.
* bsps/arm: Set MSP in ARMv7-M start codeSebastian Huber2021-04-211-0/+8
| | | | | | Set the Main Stack Pointer (MSP) to the ISR stack area end just in case we run using the Process Stack Pointer (PSP). This helps if applications are started by a boot loader.
* bsps: Remove networking driversVijay Kumar Banerjee2021-04-071-1839/+0
| | | | Update #3850
* bsps: Add missing DWARF 5 sectionsSebastian Huber2021-01-261-3/+5
| | | | Sort alphabetically.
* bsps: Support DWARF 5 sectionsSebastian Huber2021-01-251-8/+13
| | | | GCC 11 uses DWARF 5 by default.
* bsps: Use header file for GIC architecture supportSebastian Huber2020-12-231-56/+0
| | | | | | This avoids a function call overhead in the interrupt dispatching. Update #4202.
* bsps/arm: Invalidate TLB in start.SSebastian Huber2020-12-231-0/+9
| | | | Update #4202.
* bsps/arm: Clear SCTLR[M, I, A, C] in start.SSebastian Huber2020-12-231-2/+35
| | | | | | | Initialize the data and unified cache levels. Invalidate the instruction cache levels. Update #4202.
* bsps/arm: Add arm-data-cache-loop-set-way.hSebastian Huber2020-12-231-62/+9
| | | | | | This makes it possible to reuse this loop. Update #4202.
* bsps/arm: Remove optional start hook argumentsSebastian Huber2020-12-231-37/+26
| | | | | | | The start hook arguments are not used by a BSP. Removing them avoids the need for a stack during the very early system initialization. Update #4202.
* bsps/arm: Invalidate branch predictors earlierSebastian Huber2020-12-231-0/+11
| | | | | | | Make sure the branch predictors are invalidated before the first branch is executed. Update #4202.
* bsps/arm: Set VBAR in start.SSebastian Huber2020-12-231-1/+27
| | | | | | | | | | Set the VBAR to the vector table in the start section before bsp_start_hook_0() is called to earlier handle exceptions in RTEMS. Set the VBAR to the normal vector table in start.S for the main processor. Secondary processors set it in bsp_start_hook_0(). Update #4202.
* bsps: Remove gicvx_interrupt_dispatch()Sebastian Huber2020-12-161-5/+0
| | | | | | Avoid one level of indirection. Update #4202.
* bsps/arm/imx*: Fix location of shared headersChristian Mauderer2020-12-144-355/+0
| | | | | | | When moving the headers from the imx BSP to the shared area, the wrong directory has been selected. This patch fixes that problem. Update #4180
* bsps: Remove ARM GIC SGI target filterSebastian Huber2020-12-101-1/+0
| | | | | | | Remove the target filter for software-generated interrupts since this feature is not supported by the affinity routing in GICv3. Update #4202.
* bsps: Fix GICv3 arm_gic_trigger_sgi()Sebastian Huber2020-12-101-1/+1
| | | | | | | | Use the targets parameter to determine the targets of the SGI. Change targets parameter type to 32-bit to ease the parameter passing. GICv3 supports up to 16 targets. Update #4202.
* arm/cache-cp15: Support Armv8Sebastian Huber2020-12-101-13/+12
| | | | Update #4202.
* bsps: Move ARM GICv2 driver to bsps/sharedKinsey Moore2020-12-022-287/+1
| | | | | This moves the ARM GICv2 driver to bsps/shared to be usable by AArch64 code.
* bsps: Move zynq-uart to bsps/sharedKinsey Moore2020-12-022-361/+0
| | | | | This moves the zynq-uart driver from bsps/arm/shared to bsps/shared to accomodate use by AArch64 BSPs.
* bsp/imxrt: Add new BSPChristian Mauderer2020-11-201-0/+5
| | | | Update #4180
* bsps/imx: Move imx-gpio to arm/sharedChristian Mauderer2020-11-203-0/+560
| | | | Update #4180
* imx: Move imx_iomux to arm/sharedChristian Mauderer2020-11-205-0/+637
| | | | Update #4180
* bsps/arm: Sort fast text/data sectionsSebastian Huber2020-10-211-2/+2
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* bsps/arm: Add support for MPU region alignmentSebastian Huber2020-10-211-0/+21
| | | | Update #3910.
* bsps: Break out AArch32 GICv3 supportKinsey Moore2020-10-053-330/+62
| | | | | This breaks out AArch32-specific code so that the shared GICv3 code can be reused by other architectures.
* bsps: Break out AArch32 portions of GPT driverKinsey Moore2020-10-052-211/+74
| | | | | | This breaks AArch32-specific portions of the ARM GPT driver into their own file so that the generic code can be moved for reuse by other architectures.
* Move ARM PL011 UART driverKinsey Moore2020-10-051-91/+0
| | | | This UART driver is now needed for BSPs other than ARM.
* arm: Fix arm_cp15_set_translation_table_entries()Sebastian Huber2020-09-171-1/+1
| | | | | | | | In a multi-processor system we must broadcast the TLB maintenance operation to the Inner Shareable domain to ensure that the other processors update their TLB caches accordingly. Close #4068.
* bsp/xilinx-zynq: Flush TX-Buffer before initializing uartJan Sommer2020-08-221-0/+2
| | | | | Closes #4055 Closes #4056
* bsps/arm: Use _Assert()Sebastian Huber2020-08-201-3/+2
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* bsps/arm: Fix uninitialized value in generic timerChristian Mauderer2020-04-201-4/+10
| | | | | | | | _CPU_Counter_frequency() can be called by the rtems_counter initialization before arm_gt_clock_initialize() initializes the value used in _CPU_Counter_frequency(). Closes #3961.
* arm: ARMv7-M statically initialized vector tableSebastian Huber2020-04-033-36/+63
| | | | | | | Statically initialize the ARMv7-M vector table to allow a placement in ROM with read-only MPU settings. Change licence to BSD-2-Clause in some files.
* bsps/arm: Initialize priorities of PPIsSebastian Huber2020-02-241-0/+6
| | | | | | At least on GICv1 the interrupts 0 up to including 31 are so called Peripheral Private Interrupts (PPIs). We have to initialize the priority of the PPIs on secondary processors.
* score: Statically allocate idle/MPCI stacksSebastian Huber2020-02-121-3/+7
| | | | | | | Place idle and MPCI stacks into extra linker sections. This can be optionally used by applications to control the placement of the stacks. Update #3835.
* arm/xilinx-zynq: Split console driver filesSebastian Huber2020-02-122-151/+182
| | | | | This avoids to pull in via printk() the Termios support which pulls in the file system support. This fixes a spconfig02 test failure.
* bsps: Add RamEnd to linker command filesSebastian Huber2020-02-041-0/+1
| | | | Update #3838.
* bsps/arm/shared: Add GICv3 implementationKinsey Moore2020-01-172-0/+345
| | | | | | | | | This adds support for the GICv3 interrupt controller along with the redistributor to control SGIs and PPIs which wasn't present in GICv2 implementations. GICv3 implementations only optionally support memory-mapped GICC interface interaction and require system register access be implemented, so the GICC interface is accessed only through system registers.
* bsps/arm: Export bsp_start_hook_0_doneSebastian Huber2019-12-191-5/+8
| | | | Close #3789.
* bsps/arm: Unmask generic timer in interrupt handlerJeff Kubascik2019-12-051-0/+3
| | | | | Xen will mask the virtual timer before injecting the interrupt to the guest.
* bsps/arm: Add zImage boot headerJeff Kubascik2019-12-051-0/+11
| | | | | Xen currently only supports the zImage loader for 32 bit guests on ARM targets.
* bsps/arm: Add support for small pages MMUSebastian Huber2019-10-311-19/+51
| | | | | | | The small page MMU support reduces the granularity for memory settings through the MMU from 1MiB sections to 4KiB small pages. Enable it by default on the realview_pbx_a9_qemu BSP.
* arm/tlb: Fix the MP affinity check to invalidate ASIDs.Chris Johns2019-08-121-1/+9
| | | | | | - The TI's CortexA7 MP MPIDR register returns 0 Updates #3760
* arm: Select the TLB invalidate based on the core's Id variant.Chris Johns2019-07-311-6/+10
| | | | Closes #3760
* bsps/arm: Move HYP to SVC change to start.SSebastian Huber2019-07-262-78/+40
| | | | | | | | | This fixes the corruption of r3 by the call to bsp_start_arm_drop_hyp_mode(). Moving the code makes it easier to review changes in start.S. Close #3773.
* bsps/arm: Move register init to start.SSebastian Huber2019-07-262-109/+55
| | | | | | This makes it easier to review changes in start.S. Update #3773.
* bsps/arm: Remove register init for ARMv7-MSebastian Huber2019-07-261-12/+1
| | | | | | There are no known ARMv7-M chips with a dual lockstep mode. Update #3773.
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