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* bsps: Avoid unused argument in clock interruptSebastian Huber2024-03-202-26/+19
| | | | | | | | | | | Pass the parameter of the clock interrupt handler to Clock_driver_support_at_tick() and Clock_driver_timecounter_tick(). This makes it possible to use the interrupt handler argument in clock drivers. Use the interrupt handler provided by Clock_driver_support_install_isr() to avoid local delarations of Clock_isr(). Update #4862.
* bsps/arm: Use shared empty bsp_start_hook_0()Sebastian Huber2024-01-151-0/+42
| | | | Update #4982.
* bsps/arm: BSP_START_VECTOR_ADDRESS_TABLE_ALIGNMENTSebastian Huber2023-12-061-0/+4
| | | | | Add the BSP option BSP_START_VECTOR_ADDRESS_TABLE_ALIGNMENT to optionally define an alignment of the vector address table begin.
* bsps/imx*: imx_gpio from pointer to fdt propertyChristian Mauderer2023-11-281-12/+43
| | | | | | Device trees allow mixing different kinds of GPIOs in one property. For that it is usefull to only provide a pointer to an arbitrary location in the property and initialize a GPIO from that.
* arm: Fix cache support for ARM926EJ-SSebastian Huber2023-08-101-0/+26
| | | | | | | The ARM926EJ-S is an ARMv5T architecture processor and lacks some features of ARMv6 processors such as the ARM1176JZF-S. Close #4940.
* bsps/imx*: Support more GPIO controllersChristian Mauderer2023-07-241-4/+14
| | | | | | | | The imx-gpio driver used in i.MX and i.MXRT BSPs generates a name based on a fixed string. The original code only used one digit for the controller. With the 13 GPIO controllers of the i.MXRT1166, that isn't enough any more. This patch extends the name to two digits which should be enough for the next controller generations.
* arm/xilinx-zynq: Do not provide legacy APISebastian Huber2023-05-261-1/+1
| | | | | The header file <rtems/irq.h> provides a legacy API. Do not provide it by default through <bsp/irq.h>.
* bsps/arm: Use interrupt entry for IPISebastian Huber2023-05-261-6/+10
| | | | Avoid a dynamic memory allocation for the inter-processor interrupt.
* bsps/arm: Use interrupt entry for clock driverSebastian Huber2023-05-261-4/+9
| | | | Avoid a dynamic memory allocation for the clock driver interrupt.
* bsps/arm: Improve Doxygen groupsSebastian Huber2023-05-261-0/+9
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* bsps: Improve Doxygen file commentsSebastian Huber2023-05-264-9/+31
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* imx_iomux: Don't set reserved bits in PAD_CTLChristian Mauderer2023-05-221-0/+10
| | | | | | | | | On most i.MX* the upper bits in SW_PAD_CTL are reserved. On some chips, like the i.MXRT1166, they are a domain write protection. Setting them to 1 can have unexpected side effects. The device tree uses these bits for some flags. Make sure that they are not accidentally written to some value.
* Update company nameSebastian Huber2023-05-2021-21/+21
| | | | | The embedded brains GmbH & Co. KG is the legal successor of embedded brains GmbH.
* bsps/arm: Fix wordingSebastian Huber2023-03-171-1/+1
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* doxygen: Add Doxygen files to a groupSebastian Huber2023-02-161-0/+8
| | | | Update #3707.
* bsps/arm: fix Cortex-M7 systick reload valueDariusz Sabala2022-10-261-1/+1
| | | | | | | | | | | | - see ARM DUI 0646C Arm Cortex-M7 Devices Generic User Guide "The RELOAD value is calculated according to its use. For example, to generate a multi-shot timer with a period of N processor clock cycles, use a RELOAD value of N-1. If the SysTick interrupt is required every 100 clock pulses, set RELOAD to 99." - see routines used in CMSIS project for reference Close #4746.
* bsps/arm: Mark functions in start.SSebastian Huber2022-09-221-0/+2
| | | | | | | Add the function type to _start() and bsp_start_hook_0_done() so that the linker can generate ARM/Thumb interworking code. Update #4202.
* bsps/arm: Add comment about banked FIQ registersSebastian Huber2022-09-221-0/+1
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* bsps: Fix .data.rel.ro placementSebastian Huber2022-08-121-1/+1
| | | | | | | The .data.rel.ro* linker input section pattern accidentally matches with writeable data those symbol name starts with "ro". Close #4701.
* bsps: Sort .noinit* sectionsSebastian Huber2022-07-151-1/+1
| | | | | | | | Sort the .noinit* input sections by name first, then by alignment if two sections have the same name. This allows the placement of begin/end symbols to initialize some areas with a special value. Update #4678.
* bsps/arm/shared: Change license to BSD-2Joel Sherrill2022-07-0813-39/+286
| | | | Updates #3053.
* bsps/arm: MP core timer setting off by oneChris Johns2022-06-151-1/+1
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* bsp/arm: allocate .rtemsstack on REGION_STACK instead of on REGION_WORKKarel Gardas2022-05-231-1/+1
| | | | | | | | REGION_WORK may be backed by external RAM which may not be initialized in a time we need stack to work well. E.g. code loaded in flash, stack allocated on in-cpu SRAM and data (REGION_WORK) on external SDRAM. Sponsored-By: Precidata
* bsps/arm: Fix bsp_start_memcpy() for ARMv7-ARSebastian Huber2022-03-141-0/+4
| | | | Synchronize data and instruction streams.
* bsps/arm/: Scripted embedded brains header file clean upJoel Sherrill2022-03-1017-102/+0
| | | | Updates #4625.
* build: Remove old build systemSebastian Huber2021-09-211-11/+0
| | | | | Close #3250. Close #4081.
* bsps/arm: More robust SMP startSebastian Huber2021-08-121-2/+14
| | | | | Do not continue execution on processors which are not configured to prevent the use of arbitrary memory for the initialization stack.
* bsps/irq: bsp_interrupt_facility_initialize()Sebastian Huber2021-07-271-3/+1
| | | | | | Do not return a status code in bsp_interrupt_facility_initialize() since this leads to unreachable code in bsp_interrupt_initialize(). Use RTEMS_DEBUG assertions in bsp_interrupt_facility_initialize() if necessary.
* bsps/irq: bsp_interrupt_vector_disable()Sebastian Huber2021-07-261-1/+2
| | | | | | Return a status code for bsp_interrupt_vector_disable(). Update #3269.
* bsps/irq: bsp_interrupt_vector_enable()Sebastian Huber2021-07-261-1/+2
| | | | | | Return a status code for bsp_interrupt_vector_enable(). Update #3269.
* bsps/irq: Add rtems_interrupt_is_pending()Sebastian Huber2021-07-261-0/+11
| | | | | | Add a default implementation which just returns RTEMS_UNSATISFIED. Update #3269.
* bsps/irq: Add rtems_interrupt_get_attributes()Sebastian Huber2021-07-261-0/+8
| | | | | | | Add a default implementation which clears the attributes to zero and just returns RTEMS_SUCCESSFUL for valid parameters. Update #3269.
* bsps/irq: Add rtems_interrupt_raise()Sebastian Huber2021-07-261-0/+12
| | | | | | | | | Add rtems_interrupt_raise_on() and rtems_interrupt_clear(). Add a default implementation which just returns RTEMS_UNSATISFIED for valid parameters. Update #3269.
* bsps/irq: Add rtems_interrupt_vector_is_enabled()Sebastian Huber2021-07-261-0/+11
| | | | | | | Add a default implementation which just returns RTEMS_UNSATISFIED for valid parameters. Update #3269.
* bsps/arm: Fix SMP startSebastian Huber2021-07-091-0/+6
| | | | | | | | Skip the data cache initialization if we are a secondary processor. The bug was introduced by e164df5e33608576443b4cd5923a9046358ee773 and did not show up in tests using Qemu since the data cache behaviour is not emulated.
* bsps/arm: Add start up support for ARMv6 RPi ModelsPranav Dangi2021-07-071-1/+7
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* bsps/irq: Use BSP_INTERRUPT_VECTOR_COUNTSebastian Huber2021-06-242-2/+2
| | | | | | Use BSP_INTERRUPT_VECTOR_COUNT instead of BSP_INTERRUPT_VECTOR_MAX. Update #3269.
* bsps/irq: Remove BSP_INTERRUPT_VECTOR_MINSebastian Huber2021-06-241-1/+1
| | | | | | | | | | Remove BSP_INTERRUPT_VECTOR_MIN and unconditionally let interrupt vector numbers start with zero. The BSP_INTERRUPT_VECTOR_MIN == 0 invariant was tested by the previous commit and building all BSPs. Update #3269.
* bsps: Support RTEMS_NOINIT in linkcmdsSebastian Huber2021-05-021-0/+7
| | | | Update #3866.
* bsps/arm: Set MSP in ARMv7-M start codeSebastian Huber2021-04-211-0/+8
| | | | | | Set the Main Stack Pointer (MSP) to the ISR stack area end just in case we run using the Process Stack Pointer (PSP). This helps if applications are started by a boot loader.
* bsps: Remove networking driversVijay Kumar Banerjee2021-04-071-1839/+0
| | | | Update #3850
* bsps: Add missing DWARF 5 sectionsSebastian Huber2021-01-261-3/+5
| | | | Sort alphabetically.
* bsps: Support DWARF 5 sectionsSebastian Huber2021-01-251-8/+13
| | | | GCC 11 uses DWARF 5 by default.
* bsps: Use header file for GIC architecture supportSebastian Huber2020-12-231-56/+0
| | | | | | This avoids a function call overhead in the interrupt dispatching. Update #4202.
* bsps/arm: Invalidate TLB in start.SSebastian Huber2020-12-231-0/+9
| | | | Update #4202.
* bsps/arm: Clear SCTLR[M, I, A, C] in start.SSebastian Huber2020-12-231-2/+35
| | | | | | | Initialize the data and unified cache levels. Invalidate the instruction cache levels. Update #4202.
* bsps/arm: Add arm-data-cache-loop-set-way.hSebastian Huber2020-12-231-62/+9
| | | | | | This makes it possible to reuse this loop. Update #4202.
* bsps/arm: Remove optional start hook argumentsSebastian Huber2020-12-231-37/+26
| | | | | | | The start hook arguments are not used by a BSP. Removing them avoids the need for a stack during the very early system initialization. Update #4202.
* bsps/arm: Invalidate branch predictors earlierSebastian Huber2020-12-231-0/+11
| | | | | | | Make sure the branch predictors are invalidated before the first branch is executed. Update #4202.
* bsps/arm: Set VBAR in start.SSebastian Huber2020-12-231-1/+27
| | | | | | | | | | Set the VBAR to the vector table in the start section before bsp_start_hook_0() is called to earlier handle exceptions in RTEMS. Set the VBAR to the normal vector table in start.S for the main processor. Secondary processors set it in bsp_start_hook_0(). Update #4202.
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