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authorSebastian Huber <sebastian.huber@embedded-brains.de>2020-12-21 08:08:00 +0100
committerSebastian Huber <sebastian.huber@embedded-brains.de>2020-12-23 09:19:28 +0100
commitb32fd22732ea9344bd7573c767573a3ce148c3f7 (patch)
treeb0dd44ab8840a56370913bdecdc5775a7b836d8e /bsps/arm/shared
parentbsps/arm: Remove optional start hook arguments (diff)
downloadrtems-b32fd22732ea9344bd7573c767573a3ce148c3f7.tar.bz2
bsps/arm: Add arm-data-cache-loop-set-way.h
This makes it possible to reuse this loop. Update #4202.
Diffstat (limited to 'bsps/arm/shared')
-rw-r--r--bsps/arm/shared/cache/cache-v7ar-disable-data.S71
1 files changed, 9 insertions, 62 deletions
diff --git a/bsps/arm/shared/cache/cache-v7ar-disable-data.S b/bsps/arm/shared/cache/cache-v7ar-disable-data.S
index 543a3fdaf4..a5b4b7a3d1 100644
--- a/bsps/arm/shared/cache/cache-v7ar-disable-data.S
+++ b/bsps/arm/shared/cache/cache-v7ar-disable-data.S
@@ -27,7 +27,9 @@
#include <rtems/asm.h>
-#if __ARM_ARCH >= 7 && (__ARM_ARCH_PROFILE == 65 || __ARM_ARCH_PROFILE == 82)
+#include <dev/cache/arm-data-cache-loop-set-way.h>
+
+#if __ARM_ARCH >= 7 && (__ARM_ARCH_PROFILE == 'A' || __ARM_ARCH_PROFILE == 'R')
.globl rtems_cache_disable_data
.syntax unified
@@ -53,68 +55,13 @@ FUNCTION_ENTRY(rtems_cache_disable_data)
mcr p15, 0, r1, c1, c0, 0
isb
- /* Get cache levels (LoC) from CLIDR */
- mrc p15, 1, r1, c0, c0, 1
- mov r2, r1, lsr #24
- ands r2, r2, #0x7
- beq .Ldone
-
- /* Start with level 0 */
- mov r3, #0
-
-.Lflush_level:
- /* Flush level specified by r3 */
-
- /* Check cache type */
- add r4, r3, r3, lsl #1
- lsr r5, r1, r4
- and r5, r5, #0x7
- cmp r5, #2
- blt .Lno_data_cache
-
- /* Read CCSIDR */
- lsl r4, r3, #1
- mcr p15, 2, r4, c0, c0, 0
- isb
- mrc p15, 1, r5, c0, c0, 0
-
- /* Get cache line power */
- and r6, r5, #0x7
- add r6, r6, #4
-
- /* Get ways minus one */
- mov r7, #0x3ff
- ands r7, r7, r5, lsr #3
-
- /* Get way shift */
- clz r8, r7
-
- /* Get sets minus one */
- mov r9, #0x7fff
- ands r9, r9, r5, lsr #13
-
-.Lloop_over_ways:
- mov r10, r9
-
-.Lloop_over_sets:
- orr r11, r4, r7, lsl r8
- orr r11, r11, r10, lsl r6
-
- /* Clean and invalidate by set and way */
- mcr p15, 0, r11, c7, c14, 2
-
- subs r10, r10, #1
- bge .Lloop_over_sets
- subs r7, r7, #1
- bge .Lloop_over_ways
-
-.Lno_data_cache:
- /* Next level */
- add r3, r3, #1
- cmp r2, r3
- bgt .Lflush_level
+ /*
+ * Clean and invalidate the sets and ways of all data or unified cache
+ * levels using DCCISW (Data Cache line Clean and Invalidate by
+ * Set/Way).
+ */
+ ARM_DATA_CACHE_LOOP_SET_WAY c14
-.Ldone:
/* Restore interrupts */
msr CPSR_fc, r0