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| author | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2020-09-04 20:10:57 +0200 |
|---|---|---|
| committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2020-09-17 08:20:35 +0200 |
| commit | 20d82377a679e5207328943ff5d1b3ad253d1feb (patch) | |
| tree | 469e746e617aebf76f9e38bf5702caffe00b0a65 /bsps/arm/shared | |
| parent | build: Fix multiple defintion error for i386/pc386 (diff) | |
| download | rtems-20d82377a679e5207328943ff5d1b3ad253d1feb.tar.bz2 | |
arm: Fix arm_cp15_set_translation_table_entries()
In a multi-processor system we must broadcast the TLB maintenance operation to
the Inner Shareable domain to ensure that the other processors update their TLB
caches accordingly.
Close #4068.
Diffstat (limited to 'bsps/arm/shared')
| -rw-r--r-- | bsps/arm/shared/cp15/arm-cp15-set-ttb-entries.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/bsps/arm/shared/cp15/arm-cp15-set-ttb-entries.c b/bsps/arm/shared/cp15/arm-cp15-set-ttb-entries.c index 507277dca1..976f87a36e 100644 --- a/bsps/arm/shared/cp15/arm-cp15-set-ttb-entries.c +++ b/bsps/arm/shared/cp15/arm-cp15-set-ttb-entries.c @@ -107,7 +107,7 @@ static uint32_t set_translation_table_entries( #define MPIDR_UP (1 << 30) const uint32_t mpidr = arm_cp15_get_multiprocessor_affinity(); if ((mpidr & (MPIDR_MX_FMT | MPIDR_UP)) == MPIDR_MX_FMT) { - arm_cp15_tlb_invalidate_entry_all_asids(mva); + arm_cp15_tlb_invalidate_entry_all_asids_inner_shareable(mva); } else #endif |