bsps/arm: Add support for small pages MMU

The small page MMU support reduces the granularity for memory settings
through the MMU from 1MiB sections to 4KiB small pages.

Enable it by default on the realview_pbx_a9_qemu BSP.

1 files changed, 51 insertions, 19 deletions

diff --git a/bsps/arm/shared/cp15/arm-cp15-set-ttb-entries.c b/bsps/arm/shared/cp15/arm-cp15-set-ttb-entries.c
index fae6a6ba79..507277dca1 100644
--- a/bsps/arm/shared/cp15/arm-cp15-set-ttb-entries.c
+++ b/bsps/arm/shared/cp15/arm-cp15-set-ttb-entries.c
@@ -1,8 +1,8 @@
 /*
- * Copyright (c) 2010-2013 embedded brains GmbH.  All rights reserved.
+ * Copyright (c) 2010-2019 embedded brains GmbH.  All rights reserved.
  *
  *  embedded brains GmbH
- *  Obere Lagerstr. 30
+ *  Dornierstr. 4
  *  82178 Puchheim
  *  Germany
  *  <rtems@embedded-brains.de>
@@ -14,6 +14,7 @@
 
 #include <rtems.h>
 #include <libcpu/arm-cp15.h>
+#include <bspopts.h>
 
 /*
  * Translation table modification requires to propagate
@@ -35,36 +36,67 @@ static uint32_t set_translation_table_entries(
   uint32_t section_flags
 )
 {
-  uint32_t *ttb = arm_cp15_get_translation_table_base();
-  uint32_t istart = ARM_MMU_SECT_GET_INDEX(begin);
-  uint32_t iend = ARM_MMU_SECT_GET_INDEX(ARM_MMU_SECT_MVA_ALIGN_UP(end));
-  uint32_t index_mask = (1U << (32 - ARM_MMU_SECT_BASE_SHIFT)) - 1U;
-  uint32_t ctrl;
+  uint32_t *ttb;
+#ifdef ARM_MMU_USE_SMALL_PAGES
+  uint32_t *pt;
+  uint32_t flags;
+#endif
+  uint32_t istart;
+  uint32_t iend;
+  uint32_t index_mask;
   uint32_t section_flags_of_first_entry;
   uint32_t i;
-  void *first_ttb_addr;
-  void *last_ttb_end;
+  uint32_t *modified_begin;
+  size_t modified_size;
 
-  ctrl = arm_cp15_get_control();
-  section_flags_of_first_entry = ttb [istart];
-  last_ttb_end = first_ttb_addr = ttb + istart;
+  ttb = arm_cp15_get_translation_table_base();
+#ifdef ARM_MMU_USE_SMALL_PAGES
+  pt = &ttb[ARM_MMU_TRANSLATION_TABLE_ENTRY_COUNT];
+  istart = ARM_MMU_SMALL_PAGE_GET_INDEX(begin);
+  iend = ARM_MMU_SMALL_PAGE_GET_INDEX(ARM_MMU_SMALL_PAGE_MVA_ALIGN_UP(end));
+  index_mask = (1U << (32 - ARM_MMU_SMALL_PAGE_BASE_SHIFT)) - 1U;
+  section_flags_of_first_entry = ARM_MMU_SMALL_PAGE_FLAGS_TO_SECT(pt[istart])
+    | ARM_MMU_PAGE_TABLE_FLAGS_TO_SECT(ttb[ARM_MMU_SECT_GET_INDEX(begin)]);
+  modified_begin = &pt[istart];
+  flags = ARM_MMU_SECT_FLAGS_TO_SMALL_PAGE(section_flags);
+#else
+  istart = ARM_MMU_SECT_GET_INDEX(begin);
+  iend = ARM_MMU_SECT_GET_INDEX(ARM_MMU_SECT_MVA_ALIGN_UP(end));
+  index_mask = (1U << (32 - ARM_MMU_SECT_BASE_SHIFT)) - 1U;
+  section_flags_of_first_entry = ttb[istart];
+  modified_begin = &ttb[istart];
+#endif
+  modified_size = 0;
 
   for ( i = istart; i != iend; i = (i + 1U) & index_mask ) {
-    uint32_t addr = i << ARM_MMU_SECT_BASE_SHIFT;
+    uint32_t pa;
 
-    ttb [i] = addr | section_flags;
-    last_ttb_end = ttb + i + 1;
+#ifdef ARM_MMU_USE_SMALL_PAGES
+    pa = i << ARM_MMU_SMALL_PAGE_BASE_SHIFT;
+    pt[i] = pa | flags;
+    modified_size += ARM_MMU_SMALL_PAGE_TABLE_ENTRY_SIZE;
+#else
+    pa = i << ARM_MMU_SECT_BASE_SHIFT;
+    ttb[i] = pa | section_flags;
+    modified_size += ARM_MMU_TRANSLATION_TABLE_ENTRY_SIZE;
+#endif
   }
 
-  if ( ctrl & (ARM_CP15_CTRL_C | ARM_CP15_CTRL_M ) ) {
-    rtems_cache_flush_multiple_data_lines(first_ttb_addr,
-                last_ttb_end - first_ttb_addr);
+  if ((arm_cp15_get_control() & (ARM_CP15_CTRL_C | ARM_CP15_CTRL_M)) != 0) {
+    rtems_cache_flush_multiple_data_lines(modified_begin, modified_size);
   }
 
   _ARM_Data_synchronization_barrier();
 
   for ( i = istart; i != iend; i = (i + 1U) & index_mask ) {
-    void *mva = (void *) (i << ARM_MMU_SECT_BASE_SHIFT);
+    void *mva;
+
+#ifdef ARM_MMU_USE_SMALL_PAGES
+    mva = (void *) (i << ARM_MMU_SMALL_PAGE_BASE_SHIFT);
+#else
+    mva = (void *) (i << ARM_MMU_SECT_BASE_SHIFT);
+#endif
+
 #if defined(__ARM_ARCH_7A__)
     /*
      * Bit 31 needs to be 1 to indicate the register implements the