| Commit message (Collapse) | Author | Age | Files | Lines |
|
|
|
|
|
| |
This avoids a function call overhead in the interrupt dispatching.
Update #4202.
|
|
|
|
| |
Update #4202.
|
|
|
|
|
|
|
| |
Initialize the data and unified cache levels. Invalidate the
instruction cache levels.
Update #4202.
|
|
|
|
|
|
| |
This makes it possible to reuse this loop.
Update #4202.
|
|
|
|
|
|
|
| |
The start hook arguments are not used by a BSP. Removing them avoids
the need for a stack during the very early system initialization.
Update #4202.
|
|
|
|
|
|
|
| |
Make sure the branch predictors are invalidated before the first branch
is executed.
Update #4202.
|
|
|
|
|
|
|
|
|
|
| |
Set the VBAR to the vector table in the start section before
bsp_start_hook_0() is called to earlier handle exceptions in RTEMS.
Set the VBAR to the normal vector table in start.S for the main
processor. Secondary processors set it in bsp_start_hook_0().
Update #4202.
|
|
|
|
|
|
| |
Avoid one level of indirection.
Update #4202.
|
|
|
|
|
|
|
| |
When moving the headers from the imx BSP to the shared area, the wrong
directory has been selected. This patch fixes that problem.
Update #4180
|
|
|
|
|
|
|
| |
Remove the target filter for software-generated interrupts since this
feature is not supported by the affinity routing in GICv3.
Update #4202.
|
|
|
|
|
|
|
|
| |
Use the targets parameter to determine the targets of the SGI. Change
targets parameter type to 32-bit to ease the parameter passing. GICv3
supports up to 16 targets.
Update #4202.
|
|
|
|
| |
Update #4202.
|
|
|
|
|
| |
This moves the ARM GICv2 driver to bsps/shared to be usable by AArch64
code.
|
|
|
|
|
| |
This moves the zynq-uart driver from bsps/arm/shared to bsps/shared to
accomodate use by AArch64 BSPs.
|
|
|
|
| |
Update #4180
|
|
|
|
| |
Update #4180
|
|
|
|
| |
Update #4180
|
| |
|
|
|
|
| |
Update #3910.
|
|
|
|
|
| |
This breaks out AArch32-specific code so that the shared GICv3 code can
be reused by other architectures.
|
|
|
|
|
|
| |
This breaks AArch32-specific portions of the ARM GPT driver into their
own file so that the generic code can be moved for reuse by other
architectures.
|
|
|
|
| |
This UART driver is now needed for BSPs other than ARM.
|
|
|
|
|
|
|
|
| |
In a multi-processor system we must broadcast the TLB maintenance operation to
the Inner Shareable domain to ensure that the other processors update their TLB
caches accordingly.
Close #4068.
|
|
|
|
|
| |
Closes #4055
Closes #4056
|
| |
|
|
|
|
|
|
|
|
| |
_CPU_Counter_frequency() can be called by the rtems_counter
initialization before arm_gt_clock_initialize() initializes the value
used in _CPU_Counter_frequency().
Closes #3961.
|
|
|
|
|
|
|
| |
Statically initialize the ARMv7-M vector table to allow a placement in
ROM with read-only MPU settings.
Change licence to BSD-2-Clause in some files.
|
|
|
|
|
|
| |
At least on GICv1 the interrupts 0 up to including 31 are so called
Peripheral Private Interrupts (PPIs). We have to initialize the
priority of the PPIs on secondary processors.
|
|
|
|
|
|
|
| |
Place idle and MPCI stacks into extra linker sections. This can be
optionally used by applications to control the placement of the stacks.
Update #3835.
|
|
|
|
|
| |
This avoids to pull in via printk() the Termios support which pulls in
the file system support. This fixes a spconfig02 test failure.
|
|
|
|
| |
Update #3838.
|
|
|
|
|
|
|
|
|
| |
This adds support for the GICv3 interrupt controller along with the
redistributor to control SGIs and PPIs which wasn't present in GICv2
implementations. GICv3 implementations only optionally support
memory-mapped GICC interface interaction and require system register
access be implemented, so the GICC interface is accessed only
through system registers.
|
|
|
|
| |
Close #3789.
|
|
|
|
|
| |
Xen will mask the virtual timer before injecting the interrupt to the
guest.
|
|
|
|
|
| |
Xen currently only supports the zImage loader for 32 bit guests on ARM
targets.
|
|
|
|
|
|
|
| |
The small page MMU support reduces the granularity for memory settings
through the MMU from 1MiB sections to 4KiB small pages.
Enable it by default on the realview_pbx_a9_qemu BSP.
|
|
|
|
|
|
| |
- The TI's CortexA7 MP MPIDR register returns 0
Updates #3760
|
|
|
|
| |
Closes #3760
|
|
|
|
|
|
|
|
|
| |
This fixes the corruption of r3 by the call to
bsp_start_arm_drop_hyp_mode().
Moving the code makes it easier to review changes in start.S.
Close #3773.
|
|
|
|
|
|
| |
This makes it easier to review changes in start.S.
Update #3773.
|
|
|
|
|
|
| |
There are no known ARMv7-M chips with a dual lockstep mode.
Update #3773.
|
|
|
|
| |
Closes #3762
|
| |
|
| |
|
|
|
|
| |
Use _SMP_Multicast_action() instead.
|
|
|
|
|
|
| |
This driver will be shared with the xilinx-zynqmp BSP.
Update #3682.
|
| |
|
|
|
|
| |
Update #3706.
|
|
|
|
| |
Update #3706.
|
|
|
|
|
|
|
|
|
|
| |
- Use CamelCase as it is not used in our C code. Enables simple search and
replace.
- Prefix with "RTEMS" to aid deployment and integration. It aids
searching and sorting.
Update #3706.
|