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* score/cpu/mips: Change license to BSD-2Joel Sherrill2022-02-281-3/+22
| | | | Updates #3053.
* score: Canonicalize _CPU_Fatal_halt()Sebastian Huber2021-07-281-0/+13
| | | | | | | | Move _CPU_Fatal_halt() declaration to <rtems/score/cpuimpl.h> and make sure it is a proper declaration of a function which does not return. Fix the type of the error code. If necessary, add the implementation to cpu.c. Implementing _CPU_Fatal_halt() as a function makes it possible to wrap this function for example to fully test _Terminate().
* Remove superfluous <rtems/score/wkspace.h> includesSebastian Huber2021-04-201-1/+0
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* Remove superfluous <rtems/system.h> includesSebastian Huber2019-03-141-1/+0
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* Rework initialization and interrupt stack supportSebastian Huber2018-06-271-5/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Statically initialize the interrupt stack area (_Configuration_Interrupt_stack_area_begin, _Configuration_Interrupt_stack_area_end, and _Configuration_Interrupt_stack_size) via <rtems/confdefs.h>. Place the interrupt stack area in a special section ".rtemsstack.interrupt". Let BSPs define the optimal placement of this section in their linker command files (e.g. in a fast on-chip memory). This change makes makes the CPU_HAS_SOFTWARE_INTERRUPT_STACK and CPU_HAS_HARDWARE_INTERRUPT_STACK CPU port defines superfluous, since the low level initialization code has all information available via global symbols. This change makes the CPU_ALLOCATE_INTERRUPT_STACK CPU port define superfluous, since the interrupt stacks are allocated by confdefs.h for all architectures. There is no need for BSP-specific linker command file magic (except the section placement), see previous ARM linker command file as a bad example. Remove _CPU_Install_interrupt_stack(). Initialize the hardware interrupt stack in _CPU_Initialize() if necessary (e.g. m68k_install_interrupt_stack()). The optional _CPU_Interrupt_stack_setup() is still useful to customize the registration of the interrupt stack area in the per-CPU information. The initialization stack can reuse the interrupt stack, since * interrupts are disabled during the sequential system initialization, and * the boot_card() function does not return. This stack resuse saves memory. Changes per architecture: arm: * Mostly replace the linker symbol based configuration of stacks with the standard <rtems/confdefs.h> configuration via CONFIGURE_INTERRUPT_STACK_SIZE. The size of the FIQ, ABT and UND mode stack is still defined via linker symbols. These modes are rarely used in applications and the default values provided by the BSP should be sufficient in most cases. * Remove the bsp_processor_count linker symbol hack used for the SMP support. This is possible since the interrupt stack area is now allocated by the linker and not allocated from the heap. This makes some configure.ac stuff obsolete. Remove the now superfluous BSP variants altcycv_devkit_smp and realview_pbx_a9_qemu_smp. bfin: * Remove unused magic linker command file allocation of initialization stack. Maybe a previous linker command file copy and paste problem? In the start.S the initialization stack is set to a hard coded value. lm32, m32c, mips, nios2, riscv, sh, v850: * Remove magic linker command file allocation of initialization stack. Reuse interrupt stack for initialization stack. m68k: * Remove magic linker command file allocation of initialization stack. Reuse interrupt stack for initialization stack. powerpc: * Remove magic linker command file allocation of initialization stack. Reuse interrupt stack for initialization stack. * Used dedicated memory region (REGION_RTEMSSTACK) for the interrupt stack on BSPs using the shared linkcmds.base (replacement for REGION_RWEXTRA). sparc: * Remove the hard coded initialization stack. Use the interrupt stack for the initialization stack on the boot processor. This saves 16KiB of RAM. Update #3459.
* mips: Avoid SCORE_EXTERNSebastian Huber2016-02-171-0/+4
| | | | Update #2559.
* score: Add Thread_Control::is_fpSebastian Huber2015-06-091-2/+10
| | | | | | | | Store the floating-point unit property in the thread control block regardless of the CPU_HARDWARE_FP and CPU_SOFTWARE_FP settings. Make sure the floating-point unit is only enabled for the corresponding multilibs. This helps targets which have a volatile only floating point context like SPARC for example.
* Change all references of rtems.com to rtems.org.Chris Johns2014-03-211-1/+1
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* Add thread-local storage (TLS) supportSebastian Huber2014-02-041-1/+2
| | | | | Tested and implemented on ARM, m68k, PowerPC and SPARC. Other architectures need more work.
* score misc: Score misc: Clean up Doxygen #9 (GCI 2012)Alex Ivanov2012-11-301-39/+7
| | | | | | | This patch is a task from GCI 2012 which improves the Doxygen comments in the RTEMS source. https://google-melange.appspot.com/gci/task/view/google/gci2012/7977211
* Remove All CVS Id Strings Possible Using a ScriptJoel Sherrill2012-05-111-2/+0
| | | | | | | | | | | | Script does what is expected and tries to do it as smartly as possible. + remove occurrences of two blank comment lines next to each other after Id string line removed. + remove entire comment blocks which only exited to contain CVS Ids + If the processing left a blank line at the top of a file, it was removed.
* PR 1993 - Convert MIPS to PIC IRQ modelJennifer Averett2012-04-041-72/+8
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* 2011-12-09 Jennifer AverettJennifer Averett2011-12-091-1/+1
| | | | * cpu.c: Correct typo.
* 2011-07-24 Joel Sherrill <joel.sherrill@oarcorp.com>Joel Sherrill2011-07-241-10/+5
| | | | | * cpu.c: Remove /*PAGE markers which were interpreted by a long dead print script.
* 2011-02-11 Ralf Corsépius <ralf.corsepius@rtems.org>Ralf Corsepius2011-02-111-1/+1
| | | | | * cpu.c, rtems/score/mips.h: Use "__asm__" instead of "asm" for improved c99-compliance.
* 2010-04-25 Joel Sherrill <joel.sherrilL@OARcorp.com>Joel Sherrill2010-04-251-0/+43
| | | | | * cpu.c, rtems/score/cpu.h: Move _CPU_Context_Initialize() to cpu.c so it is easier to make warning free.
* 2010-03-27 Joel Sherrill <joel.sherrill@oarcorp.com>Joel Sherrill2010-03-271-3/+4
| | | | * cpu.c, cpu_asm.S: Add include of config.h
* Whitespace removal.Ralf Corsepius2009-12-041-11/+11
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* 2009-02-12 Joel Sherrill <joel.sherrill@oarcorp.com>Joel Sherrill2009-02-121-1/+1
| | | | | * cpu.c, rtems/score/cpu.h: Change prototype of IDLE thread to consistently return void * and take a uintptr_t argument.
* 2009-02-11 Joel Sherrill <joel.sherrill@oarcorp.com>Joel Sherrill2009-02-111-4/+2
| | | | | | * cpu.c, rtems/score/cpu.h: Eliminate _CPU_Thread_dispatch_pointer and passing address of _Thread_Dispatch to _CPU_Initialize. Clean up comments.
* Fix typo.Ralf Corsepius2008-12-071-1/+1
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* 2008-07-31 Joel Sherrill <joel.sherrill@OARcorp.com>Joel Sherrill2008-07-311-1/+1
| | | | * cpu.c, rtems/score/cpu.h: Correct prototype of Idle threads.
* 2007-12-04 Joel Sherrill <joel.sherrill@OARcorp.com>Joel Sherrill2007-12-041-4/+0
| | | | | | * cpu.c, rtems/score/cpu.h: Move interrupt_stack_size field from CPU Table to Configuration Table. Eliminate CPU Table from all ports. Delete references to CPU Table in all forms.
* 2007-05-22 Joel Sherrill <joel.sherrill@OARcorp.com>Joel Sherrill2007-05-221-1/+0
| | | | | | | | | * score/cpu/arm/cpu.c, score/cpu/avr/cpu.c, score/cpu/bfin/cpu.c, score/cpu/c4x/cpu.c, score/cpu/h8300/cpu.c, score/cpu/i386/cpu.c, score/cpu/m68k/cpu.c, score/cpu/mips/cpu.c, score/cpu/nios2/cpu.c, score/cpu/no_cpu/cpu.c, score/cpu/sh/cpu.c, score/cpu/sparc/cpu.c, cpukit/sapi/src/exinit.c: Move copying of CPU Table to shared executive initialization.
* Added __mips==32 to fix build problems on those targets caused by the ↵Greg Menke2006-06-101-2/+2
| | | | B.Robinson patch
* B.Robinson MIPS patchGreg Menke2006-06-081-7/+14
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* 2006-03-17 Ralf Corsepius <ralf.corsepius@rtems.org>Ralf Corsepius2006-03-171-1/+5
| | | | * cpu.c (_CPU_Initialize): Add fpu initialization.
* PR 730Greg Menke2004-12-061-8/+10
| | | | | * cpu_asm.S: Collected PR 601 changes for commit to cvshead for rtems-4.7
* 2004-04-14 Ralf Corsepius <ralf_corsepius@rtems.org>Ralf Corsepius2004-04-141-5/+0
| | | | | | PR 605/bsps * cpu.c: Remove further c++ style comments having been missed in previous patch. Remove printf's entirely.
* 2004-04-09 Joel Sherrill <joel@OARcorp.com>Joel Sherrill2004-04-091-2/+2
| | | | | PR 605/bsps * cpu.c: Do not use C++ style comments.
* 2004-03-30 Ralf Corsepius <ralf_corsepius@rtems.org>Ralf Corsepius2004-03-301-4/+4
| | | | * cpu.c, rtems/score/cpu.h: Convert to using c99 fixed size types.
* 2003-09-04 Joel Sherrill <joel@OARcorp.com>Joel Sherrill2003-09-041-1/+1
| | | | | * cpu.c, cpu_asm.S, rtems/score/cpu.h, rtems/score/mips.h, rtems/score/types.h: URL for license changed.
* 2002-03-05 Greg Menke <gregory.menke@gsfc.nasa.gov>Joel Sherrill2002-03-081-0/+12
| | | | | | | | | | | | * cpu_asm.S: Added support for the debug exception vector, cleaned up the exception processing & exception return stuff. Re-added EPC in the task context structure so the gdb stub will know where a thread is executing. Should've left it there in the first place... * idtcpu.h: Added support for the debug exception vector. * cpu.c: Added ___exceptionTaskStack to hold a pointer to the stack frame in an interrupt so context switch code can get the userspace EPC when scheduling. * rtems/score/cpu.h: Re-added EPC to the task context.
* 2002-02-27 Greg Menke <gregory.menke@gsfc.nasa.gov>Joel Sherrill2002-03-011-8/+23
| | | | | | | | | | | | | | | | * cpu_asm.S: Fixed exception return address, modified FP context switch so FPU is properly enabled and also doesn't screw up the exception FP handling. * idtcpu.h: Added C0_TAR, the MIPS target address register used for returning from exceptions. * iregdef.h: Added R_TAR to the stack frame so the target address can be saved on a per-exception basis. The new entry is past the end of the frame gdb cares about, so doesn't affect gdb or cpu.h stuff. * rtems/score/cpu.h: added an #ifdef so cpu_asm.S can include it to obtain FPU defines without systax errors generated by the C defintions. * cpu.c: Improved interrupt level saves & restores.
* 2001-02-01 Greg Menke <gregory.menke@gsfc.nasa.gov>Joel Sherrill2002-02-011-18/+33
| | | | | | | | | * cpu.c: Enhancements and fixes for modifying the SR when changing the interrupt level. * cpu_asm.S: Fixed handling of FP enable bit so it is properly managed on a per-task basis, improved handling of interrupt levels, and made deferred FP contexts work on the MIPS. * rtems/score/cpu.h: Modified to support above changes.
* 2001-07-03 Joel Sherrill <joel@OARcorp.com>Joel Sherrill2001-07-031-1/+1
| | | | * cpu.c: Fixed typo.
* 2001-03-14 Joel Sherrill <joel@OARcorp.com>Joel Sherrill2001-03-141-41/+21
| | | | | | * cpu.c, rtems/score/cpu.h, rtems/score/mipstypes.h: Removed unused variable _CPU_Thread_dispatch_pointer and cleaned numerous comments.
* 2001-03-13 Joel Sherrill <joel@OARcorp.com>Joel Sherrill2001-03-141-5/+43
| | | | | | | * cpu.c, cpu_asm.S, iregdef.h, rtems/score/cpu.h, rtems/score/mips.h: Merged MIPS1 and MIPS3 code reducing the number of lines of assembly. Also reimplemented some assembly routines in C further reducing the amount of assembly and increasing maintainability.
* 2000-12-19 Joel Sherrill <joel@OARcorp.com>Joel Sherrill2000-12-191-11/+0
| | | | | * cpu.c (_CPU_Initialize): Do not initialize _ISR_Vector_table() here because it has not been allocated yet.
* 2000-12-13 Joel Sherrill <joel@OARcorp.com>Joel Sherrill2000-12-131-2/+0
| | | | | | | | * cpu.c: Removed duplicate declaration for _ISR_Vector_table. * cpu_asm.S: Removed assembly language to vector ISR handler on MIPS ISA I. Now call mips_vector_isr_handlers() in libcpu or BSP. * rtems/score/cpu.h (CPU_INTERRUPT_NUMBER_OF_VECTORS): No longer a constant -- get the real value from libcpu.
* 2000-12-13 Joel Sherrill <joel@OARcorp.com>Joel Sherrill2000-12-131-12/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * cpu_asm.h: Removed. * Makefile.am: Remove cpu_asm.h. * rtems/score/mips64orion.h: Renamed mips.h. * rtems/score/mips.h: New file, formerly mips64orion.h. Header rewritten. (mips_get_sr, mips_set_sr, mips_enable_in_interrupt_mask, mips_disable_in_interrupt_mask): New macros. * rtems/score/Makefile.am: Reflect renaming mips64orion.h. * asm.h: Include <mips.h> not <mips64orion.h>. Now includes the few defines that were in <cpu_asm.h>. * cpu.c (_CPU_ISR_Get_level): Added MIPS ISA I version of this routine. MIPS ISA 3 is still in assembly for now. (_CPU_Thread_Idle_body): Rewrote in C. * cpu_asm.S: Rewrote file header. (FRAME,ENDFRAME) now in asm.h. (_CPU_ISR_Get_level): Removed ISA I version and rewrote in C. (_CPU_ISR_Set_level): Removed ISA I version and rewrote in C. (_CPU_Context_switch): MIPS ISA I now manages preserves SR_IEC and leaves other bits in SR alone on task switch. (mips_enable_interrupts,mips_disable_interrupts, mips_enable_global_interrupts,mips_disable_global_interrupts, disable_int, enable_int): Removed. (mips_get_sr): Rewritten as C macro. (_CPU_Thread_Idle_body): Rewritten in C. (init_exc_vecs): Rewritten in C as mips_install_isr_entries() and placed in libcpu. (exc_tlb_code, exc_xtlb_code, exc_cache_code, exc_norm_code): Moved to libcpu/mips/shared/interrupts. (general): Cleaned up comment blocks and #if 0 areas. * idtcpu.h: Made ifdef report an error. * iregdef.h: Removed warning. * rtems/score/cpu.h (CPU_INTERRUPT_NUMBER_OF_VECTORS): Now a variable number defined by libcpu. (_CPU_ISR_Disable, _CPU_ISR_Enable): Rewritten to use new routines to access SR. (_CPU_ISR_Set_level): Rewritten as macro for ISA I. (_CPU_Context_Initialize): Honor ISR level in task initialization. (_CPU_Fatal_halt): Use new _CPU_ISR_Disable() macro.
* 2000-10-24 Alan Cudmore <alanc@linuxstart.com> andJoel Sherrill2000-10-241-14/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | Joel Sherrill <joel@OARcorp.com> * This is a major reworking of the mips64orion port to use gcc predefines as much as possible and a big push to multilib the mips port. The mips64orion port was copied/renamed to mips to be more like other GNU tools. Alan did most of the technical work of determining how to map old macro names used by the mips64orion port to standard compiler macro definitions. Joel did the merge with CVS magic to keep individual file history and did the BSP modifications. Details follow: * Makefile.am: idtmon.h in mips64orion port not present. * asm.h: MIPS64ORION replaced with MIPS. Frame setup macros added. * cpu.c: Comments added. * cpu_asm.S: Conditionals changed. MIPS ISA level 1 support added. First attempt at exception/interrupt processing for ISA level 1 and minus any use of IDT/MON added. * idtcpu.h: Conditionals changed to use gcc predefines. * iregdef.h: Ditto. * cpu_asm.h: No real change. Merger required commit. * rtems/Makefile.am: Ditto. * rtems/score/Makefile.am: Ditto. * rtems/score/cpu.h: Change MIPS64ORION to MIPS. * rtems/score/mips64orion.h: Change MIPS64ORION to MIPS. Convert from using RTEMS_CPU_MODEL to gcc predefines to figre things out.
* Removed no cpu references.Joel Sherrill2000-07-111-1/+1
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* Updated copyright notice.Joel Sherrill1999-11-171-2/+1
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* updated copyright to 1998Joel Sherrill1998-02-171-1/+1
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* Fixed typo in the pointer to the license terms.Joel Sherrill1997-10-081-2/+2
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* headers updated to reflect new style copyright notice as partJoel Sherrill1997-04-221-5/+5
| | | | of switching to the modified GNU GPL.
* commented out sccs_id to eliminate warning.Joel Sherrill1997-04-071-3/+6
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* added $Id$ to file headersJoel Sherrill1996-09-111-1/+1
| | | | cpu.h: added prototype for _CPU_ISR_Get_level()
* new file for MIPS port by Craig Lebakken (lebakken@minn.net) andJoel Sherrill1996-09-061-0/+216
Derrick Ostertag (ostertag@transition.com).
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