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authorRalf Corsepius <ralf.corsepius@rtems.org>2009-12-04 05:25:30 +0000
committerRalf Corsepius <ralf.corsepius@rtems.org>2009-12-04 05:25:30 +0000
commit5bb38e15667c03ef44420cdeb7889db42649ece3 (patch)
tree82cf091802d6c2895f2a69ee74ad7373ec77607a /cpukit/score/cpu/mips/cpu.c
parent42e243eeef1dd20a5053dbe53ed9ef5eebd7d181 (diff)
downloadrtems-5bb38e15667c03ef44420cdeb7889db42649ece3.tar.bz2
Whitespace removal.
Diffstat (limited to 'cpukit/score/cpu/mips/cpu.c')
-rw-r--r--cpukit/score/cpu/mips/cpu.c22
1 files changed, 11 insertions, 11 deletions
diff --git a/cpukit/score/cpu/mips/cpu.c b/cpukit/score/cpu/mips/cpu.c
index 0b6b2cee69..863f14655c 100644
--- a/cpukit/score/cpu/mips/cpu.c
+++ b/cpukit/score/cpu/mips/cpu.c
@@ -8,7 +8,7 @@
* should still work OK.
*
* Conversion to MIPS port by Alan Cudmore <alanc@linuxstart.com> and
- * Joel Sherrill <joel@OARcorp.com>.
+ * Joel Sherrill <joel@OARcorp.com>.
*
* These changes made the code conditional on standard cpp predefines,
* merged the mips1 and mips3 code sequences as much as possible,
@@ -29,7 +29,7 @@
* copies, and that the name of Transition Networks not be used in
* advertising or publicity pertaining to distribution of the
* software without specific, written prior permission.
- * Transition Networks makes no representations about the
+ * Transition Networks makes no representations about the
* suitability of this software for any purpose.
*
* COPYRIGHT (c) 1989-2001.
@@ -49,19 +49,19 @@
-/*
-** Exception stack frame pointer used in cpu_asm to pass the exception stack frame
+/*
+** Exception stack frame pointer used in cpu_asm to pass the exception stack frame
** address to the context switch code.
*/
#if (__mips == 1) || (__mips == 32)
typedef uint32_t ESF_PTR_TYPE;
-#elif (__mips == 3)
+#elif (__mips == 3)
typedef uint64_t ESF_PTR_TYPE;
#else
#error "unknown MIPS ISA"
#endif
-ESF_PTR_TYPE __exceptionStackFrame = 0;
+ESF_PTR_TYPE __exceptionStackFrame = 0;
@@ -124,12 +124,12 @@ void _CPU_ISR_Set_level( uint32_t new_level )
{
unsigned int sr, srbits;
- /*
- ** mask off the int level bits only so we can
+ /*
+ ** mask off the int level bits only so we can
** preserve software int settings and FP enable
** for this thread. Note we don't force software ints
** enabled when changing level, they were turned on
- ** when this task was created, but may have been turned
+ ** when this task was created, but may have been turned
** off since, so we'll just leave them alone.
*/
@@ -158,7 +158,7 @@ void _CPU_ISR_Set_level( uint32_t new_level )
mips_set_sr(sr); * first disable ie bit (recommended) *
}
*/
-
+
#elif __mips == 1
mips_set_sr( (sr & ~SR_IEC) );
srbits = sr & ~(0xfc00 | SR_IEC);
@@ -184,7 +184,7 @@ void _CPU_ISR_Set_level( uint32_t new_level )
* Output parameters: NONE
*
*/
-
+
void _CPU_ISR_install_raw_handler(
uint32_t vector,
proc_ptr new_handler,