2000-10-24 Alan Cudmore <alanc@linuxstart.com> and

	Joel Sherrill <joel@OARcorp.com>

	* This is a major reworking of the mips64orion port to use
	gcc predefines as much as possible and a big push to multilib
	the mips port.  The mips64orion port was copied/renamed to mips
	to be more like other GNU tools.  Alan did most of the technical
	work of determining how to map old macro names used by the mips64orion
	port to standard compiler macro definitions.  Joel did the merge
	with CVS magic to keep individual file history and did the BSP
	modifications. Details follow:
	* Makefile.am: idtmon.h in mips64orion port not present.
	* asm.h: MIPS64ORION replaced with MIPS. Frame setup macros added.
	* cpu.c: Comments added.
	* cpu_asm.S: Conditionals changed.  MIPS ISA level 1 support added.
	First attempt at exception/interrupt processing for ISA level 1
	and minus any use of IDT/MON added.
	* idtcpu.h: Conditionals changed to use gcc predefines.
	* iregdef.h: Ditto.
	* cpu_asm.h: No real change.  Merger required commit.
	* rtems/Makefile.am: Ditto.
	* rtems/score/Makefile.am: Ditto.
	* rtems/score/cpu.h: Change MIPS64ORION to MIPS.
	* rtems/score/mips64orion.h: Change MIPS64ORION to MIPS.  Convert
	from using RTEMS_CPU_MODEL to gcc predefines to figre things out.

1 files changed, 16 insertions, 14 deletions

diff --git a/cpukit/score/cpu/mips/cpu.c b/cpukit/score/cpu/mips/cpu.c
index 1d56652622..db9ae911b4 100644
--- a/cpukit/score/cpu/mips/cpu.c
+++ b/cpukit/score/cpu/mips/cpu.c
@@ -1,22 +1,24 @@
 /*
  *  Mips CPU Dependent Source
  *
- *  Author:     Craig Lebakken <craigl@transition.com>
+ *  Conversion to MIPS port by Alan Cudmore <alanc@linuxstart.com> and
+ *           Joel Sherrill <joel@OARcorp.com>.
  *
- *  COPYRIGHT (c) 1996 by Transition Networks Inc.
+ *  Original MIP64ORION port by Craig Lebakken <craigl@transition.com>
+ *           COPYRIGHT (c) 1996 by Transition Networks Inc.
  *
- *  To anyone who acknowledges that this file is provided "AS IS"
- *  without any express or implied warranty:
- *      permission to use, copy, modify, and distribute this file
- *      for any purpose is hereby granted without fee, provided that
- *      the above copyright notice and this notice appears in all
- *      copies, and that the name of Transition Networks not be used in
- *      advertising or publicity pertaining to distribution of the
- *      software without specific, written prior permission.
- *      Transition Networks makes no representations about the suitability
- *      of this software for any purpose.
+ *         To anyone who acknowledges that this file is provided "AS IS"
+ *         without any express or implied warranty:
+ *             permission to use, copy, modify, and distribute this file
+ *             for any purpose is hereby granted without fee, provided that
+ *             the above copyright notice and this notice appears in all
+ *             copies, and that the name of Transition Networks not be used in
+ *             advertising or publicity pertaining to distribution of the
+ *             software without specific, written prior permission.
+ *             Transition Networks makes no representations about the 
+ *             suitability of this software for any purpose.
  *
- *  Derived from source copyrighted as follows:
+ *  Derived from c/src/exec/score/cpu/no_cpu/cpu.c:
  *
  *  COPYRIGHT (c) 1989-1999.
  *  On-Line Applications Research Corporation (OAR).
@@ -124,7 +126,7 @@ void _CPU_ISR_install_raw_handler(
    *  This is where we install the interrupt handler into the "raw" interrupt
    *  table used by the CPU to dispatch interrupt handlers.
    */
-
+/* Q: This will become necessary for Non IDT/Sim use...*/
 #if 0 /* not necessary */
 /* use IDT/Sim to set interrupt vector.  Needed to co-exist with debugger. */
    add_ext_int_func( vector, new_handler );