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When the switch to waf occurred, the SMP support in i386 was left out
causing it to accumulate a minor amount of cruft. This enables SMP for
the i386 BSPs that support it and updates them for the API drift that
has occurred since the change.
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sse_test.c was deliberarely NOT changed.
Updates #3053.
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Make sure that the esp is restored before the eflags register.
When the init task is initially restored, system interrupts are activated when the
eflags register is loaded.
If the esp register still points to an address in the interrupt stack
area (from early system initlization) the ISR might overwrite its own
stack.
Closes #4031
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Uses similar flow in cpu_asm.S for i386 as for arm.
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Create a GS segment in the GDT for each processor for storing TLS.
This makes the GDT in startAP.S obsolete as all processors now share the
same GDT, which is passed to each AP at startup.
The correct segment for each processor is calculated in cpu_asm.S.
Update #3335
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Update #2468.
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We must not alter the is executing indicator in
_CPU_Context_Initialize() since this would cause an invalid state during
a self restart.
The is executing indicator must be valid at creation time since
otherwise _Thread_Kill_zombies() uses an undefined value for not started
threads. This could result in a system life lock.
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The current implementation of task migration in RTEMS has some
implications with respect to the interrupt latency. It is crucial to
preserve the system invariant that a task can execute on at most one
processor in the system at a time. This is accomplished with a boolean
indicator in the task context. The processor architecture specific
low-level task context switch code will mark that a task context is no
longer executing and waits that the heir context stopped execution
before it restores the heir context and resumes execution of the heir
task. So there is one point in time in which a processor is without a
task. This is essential to avoid cyclic dependencies in case multiple
tasks migrate at once. Otherwise some supervising entity is necessary to
prevent life-locks. Such a global supervisor would lead to scalability
problems so this approach is not used. Currently the thread dispatch is
performed with interrupts disabled. So in case the heir task is
currently executing on another processor then this prolongs the time of
disabled interrupts since one processor has to wait for another
processor to make progress.
It is difficult to avoid this issue with the interrupt latency since
interrupts normally store the context of the interrupted task on its
stack. In case a task is marked as not executing we must not use its
task stack to store such an interrupt context. We cannot use the heir
stack before it stopped execution on another processor. So if we enable
interrupts during this transition we have to provide an alternative task
independent stack for this time frame. This issue needs further
investigation.
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Script does what is expected and tries to do it as
smartly as possible.
+ remove occurrences of two blank comment lines
next to each other after Id string line removed.
+ remove entire comment blocks which only exited to
contain CVS Ids
+ If the processing left a blank line at the top of
a file, it was removed.
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* cpu.c, cpu_asm.S: Remove /*PAGE markers which were interpreted by a
long dead print script.
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* cpu_asm.S: Formatting.
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* cpu.c, cpu_asm.S, sse_test.c: Add include of config.h
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* cpu.c, cpu_asm.S, rtems/score/cpu.h, sse_test.c:
Added experimental SSE support.
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* score/cpu/i386/rtems/score/cpu.h:
Added #ifdef ASM constructs so that this header can be
included from assembly code.
Increased CPU_STACK_ALIGNMENT to 16 bytes. Gcc maintains
16-byte alignment and it may be a advantageous to provide
initial 16-byte alignment. When using SSE some gcc versions
may produce code that crashes if the stack is not 16-byte aligned.
Make sure _CPU_Context_Initialize() sets the thread stack
up so that it is aligned to CPU_CACHE_ALIGNMENT.
* score/cpu/i386/cpu_asm.S:
Align stack to CPU_CACHE_ALIGNMENT before calling C-code.
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* cpu_asm.S: Convert asm comments to C-comments to prevent gcc-3.4.0pre
from choking on them.
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* cpu_asm.S: Include <rtems/asm.h> instead of <asm.h>.
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* cpu.c, cpu_asm.S, rtems/score/cpu.h, rtems/score/interrupts.h:
Convert to using c99 fixed size types.
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* cpu.c, cpu_asm.S, rtems/score/cpu.h, rtems/score/i386.h,
rtems/score/idtr.h, rtems/score/interrupts.h,
rtems/score/registers.h, rtems/score/types.h: URL for license
changed.
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and not likely to become so. Comments on each configuration
are below.
+ Force CPU386 - This BSP was developed as part of the initial
port of RTEMS to the i386. This board has been unavailable
for a long time now.
+ GO32 - This BSP and some CPU code supported djgpp v1.x. This
version is now quite old. No one has stepped forward to
update the code to v2.x which may be technically impossible
anyway. More importantly, go32 has been superceded by the pc386 BSP.
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.s files to .S in conformance with GNU conventions. This is a
minor step along the way to supporting automake.
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