summaryrefslogtreecommitdiffstats
path: root/bsps/riscv (follow)
Commit message (Expand)AuthorAgeFilesLines
* bsps: Move declarations to <bsp/irq-generic.h>Sebastian Huber2024-03-276-42/+1
* bsps: Avoid unused argument in clock interruptSebastian Huber2024-03-202-9/+6
* bsps: Use new APBUART register block APISebastian Huber2023-07-142-8/+17
* bsps/grlib: Add generated headersSebastian Huber2023-07-141-0/+210
* bsps: Remove uses of BSP-specific interrupt APISebastian Huber2023-06-161-6/+0
* Update company nameSebastian Huber2023-05-2020-20/+20
* bsps/riscv: add riscv/kendrytek210 BSP variant source changesAlan Cudmore2023-03-287-6/+171
* bsps/riscv: add device tree source and device tree blob header for k210 bsp v...Alan Cudmore2023-03-282-0/+531
* bsps/riscv: Use per-CPU mtimecmp in clock driverSebastian Huber2023-03-171-26/+15
* bsps/riscv: Fix riscv_get_hart_index_by_phandle()Sebastian Huber2023-03-172-2/+10
* bsps/riscv: Make SMP start more robustSebastian Huber2023-03-172-6/+15
* doxygen: Add Doxygen files to a groupSebastian Huber2023-02-161-0/+8
* clockdrv: Add clock driver implementation groupSebastian Huber2023-01-241-2/+3
* tm27: Avoid function pointer castsSebastian Huber2023-01-241-4/+2
* riscv: Resurrect RISCV_ENABLE_HTIF_SUPPORTSebastian Huber2023-01-126-12/+30
* RISC-V: Always probe for HTIF and remove RISCV_ENABLE_HTIF_SUPPORTHesham Almatary2022-12-236-26/+18
* bsps/irq: Rename handler in dispatch tableSebastian Huber2022-12-021-2/+2
* bsps/riscv: Simplify PLIC supportSebastian Huber2022-11-231-28/+30
* bsps/riscv: Fix PLIC enable register countSebastian Huber2022-11-231-3/+5
* bsps/riscv: Add riscv_plic_cpu_0_init()Sebastian Huber2022-11-231-13/+23
* bsps/riscv: Fix bsp_fdt_map_intr()Sebastian Huber2022-11-231-1/+1
* bsps/riscv: Change license to BSD-2 for files with Gaisler copyrightDaniel Cederman2022-11-145-12/+90
* bsps/riscv: Fix software interrupt dispatchingSebastian Huber2022-11-111-2/+4
* bsps/noel: Fix interrupt supportSebastian Huber2022-11-111-0/+2
* bsps/riscv: Fix PLIC enable register countSebastian Huber2022-11-101-2/+2
* bsps/riscv: Skip init on not configured processorsSebastian Huber2022-11-101-0/+11
* bsps/riscv: Simplify riscv_plic_init()Sebastian Huber2022-11-101-30/+39
* bsps/riscv: Simplify riscv_clint_init()Sebastian Huber2022-11-101-14/+25
* bsps/riscv: Add tm27 supportSebastian Huber2022-11-101-1/+136
* bsps/riscv: Always dispatch software interruptsSebastian Huber2022-11-101-3/+2
* bsps/riscv: bsp_interrupt_get/set_affinity()Sebastian Huber2022-11-101-13/+6
* bsps/riscv: bsp_interrupt_raise_on()Sebastian Huber2022-11-101-4/+20
* bsps/riscv: bsp_interrupt_is_pending()Sebastian Huber2022-11-101-2/+25
* bsps/riscv: bsp_interrupt_get_attributes()Sebastian Huber2022-11-101-0/+15
* bsps/riscv: Improve bsp_interrupt_vector_disable()Sebastian Huber2022-11-101-0/+8
* bsps/riscv: Improve bsp_interrupt_vector_enable()Sebastian Huber2022-11-101-0/+8
* bsps/riscv: bsp_interrupt_vector_is_enabled()Sebastian Huber2022-11-101-2/+47
* bsps/riscv: bsp_interrupt_is_valid_vector()Sebastian Huber2022-11-102-1/+18
* bsps/riscv: Use start data for objectSebastian Huber2022-11-041-0/+6
* bsps/riscv: Workaround for sporadic linker issuesSebastian Huber2022-10-281-0/+1
* bsps: Improve riscv console FDT parsingAlan Cudmore2022-10-141-9/+5
* riscv: Move functions to avoid build issuesSebastian Huber2022-10-141-10/+0
* bsps/riscv: Add Microchip PolarFire SoC BSP variantPadmarao Begari2022-09-208-4/+132
* bsps/riscv: Add device tree blobPadmarao Begari2022-09-202-0/+967
* bsps/riscv/riscv: Fix fe310_uart_readAlan Cudmore2022-09-191-2/+5
* bsp/riscv: Add NOEL-V BSPMartin Aberg2022-09-068-0/+469
* bsp/riscv: Work area size based on /memory node in fdtDaniel Cederman2022-09-061-0/+144
* riscv: Use zicsr architecture extensionSebastian Huber2022-02-252-1/+8
* bsps/riscv: Add missing includeSebastian Huber2022-02-251-0/+1
* bsp_specs: Delete last remnants of these.Joel Sherrill2021-11-292-0/+0
generated by cgit v1.2.3 (git 2.25.1) at 2024-04-25 10:56:34 +0000