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* dev/irq: Improve Doxgyen group assignmentsSebastian Huber2024-04-165-17/+51
| | | | | Make the GIC interrupt controller support a subgroup of the generic interrupt controller support.
* dev/serial: Add ZYNQ_UART_[01]_BASE_ADDRSebastian Huber2024-04-042-0/+132
| | | | This helps to provide a shared implementation of the kernel I/O support.
* dev/serial: Simplify some Zynq UART functionsSebastian Huber2024-03-272-23/+20
| | | | | | Make the initialization and polled functions independent of the Termios context. This helps to implement the kernel I/O support without a dependency on the Termios framework.
* bsps: Move declarations to <bsp/irq-generic.h>Sebastian Huber2024-03-271-11/+0
| | | | | | | | | | | Move declarations of bsp_interrupt_get_affinity() and bsp_interrupt_set_affinity() to <bsp/irq-generic.h>. Canonicalize the <bsp/irq.h> includes. Implement bsp_interrupt_get_affinity() and bsp_interrupt_set_affinity() only if needed (usually RTEMS_SMP). Provide stub implementations for i386 to fix build errors.
* dev/irq: Optional arm_gic_irq_processor_count()Sebastian Huber2024-03-201-0/+2
| | | | Provide arm_gic_irq_processor_count() only in SMP configurations.
* bsps/shared/xnandpsu: Add opportunistic page cacheKinsey Moore2024-03-111-0/+9
| | | | | | | | Add an opportunistic page cache to the xnandpsu driver since it does not implement partial page reads and common filesystem access patterns perform multiple reads from the same page. This has been seen to provide a 10x speedup to read speeds and a 2x speedup on first initialization when used with JFFS2.
* tm27: Add optional TM27_INTERRUPT_VECTOR_DEFAULTSebastian Huber2023-12-191-0/+2
| | | | | | | Let the BSP define TM27_INTERRUPT_VECTOR_DEFAULT to more efficiently and reliably get the TM27 default interrupt vector. Update #3716.
* bsps/xnandpsu: Allow manipulation of BBTKinsey Moore2023-12-141-0/+46
| | | | | | Expose functions to directly manipulate the bad block table (BBT). These functions are necessary to correct possible BBT corruption caused by bugs in the BBT management layer.
* bsps/arm: Add BSP for ZynqMP RPUPhilip Kirkpatrick2023-11-201-0/+3
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* bsps/clock: Import Xilinx TTC hardware definitionsKinsey Moore2023-11-202-0/+231
| | | | | | This imports the TTC hardware definitions for the triple timer counters on various Xilinx platforms. This was imported as specified in the VERSION file in this commit.
* bsps/xqspipsu: Add SFDP config space read abilityKinsey Moore2023-09-232-0/+21
| | | | | This adds a function to allow reading of the SFDP configuration space that describes attributes of NOR flash chips.
* bsps/xqspipsu: Break out RDIDKinsey Moore2023-09-231-0/+15
| | | | | Expose a function to read the NOR flash chip ID information beyond the minimum 3 bytes for the lookup table.
* bsps/xqspipsu: Handle SMP systems properlyKinsey Moore2023-06-221-0/+3
| | | | | | | The NOR driver was not written with SMP systems and caching in mind. This makes the IsBusy flag volatile for updates across cores and introduces cache flushing and invalidation where necessary for data manipulated by the DMA engine in the QSPI peripheral.
* bsps/xqspipsu: Use device information from the FCTKinsey Moore2023-06-081-0/+24
| | | | | | Instead of statically defining the device parameters, use the device information available via the NOR device layer's Flash Configuration Table.
* bsps/xqspipsu: Correct s25fl512s flash definitionKinsey Moore2023-06-081-2/+2
| | | | | The definition for the s25fl512s flash chip is incorrect. This updates the sector size and page size values to match the datasheet.
* bsps/xqspipsu: Ensure NOR writes alignKinsey Moore2023-06-081-1/+24
| | | | | | | This change causes NOR writes to be broken according to page boundaries. Writes across page boundaries cause the writes beyond the boundary to fail silently. This also introduces a new function that will explicitly write pages.
* termios: Add <rtems/termiosdevice.h>Sebastian Huber2023-05-311-1/+1
| | | | | | | Add <rtems/termiosdevice.h> which does not depend on <rtems/libio.h> to provide rtems_termios_device_context and rtems_termios_device_handler. For polled serial device drivers, this removes a header file dependency to the full file system support.
* bsps/arm: Use interrupt entry for <tm27.h>Sebastian Huber2023-05-261-18/+34
| | | | | Avoid a dynamic memory allocation for the <tm27.h> interrupts. Replace assert() with _Assert().
* Update company nameSebastian Huber2023-05-2011-11/+11
| | | | | The embedded brains GmbH & Co. KG is the legal successor of embedded brains GmbH.
* bsps/xqspipsu: Add support for reading ECCKinsey Moore2023-03-222-0/+30
| | | | | This adds a helper function to read the ECC status for an ECC unit in SPI-attached NOR memory.
* bsps/xnandpsu: Allow use of both chip selectsKinsey Moore2023-03-151-0/+4
| | | | | | By default, the Xilinx NAND driver does not probe the second chip select. This alteration allows the second half of chips to be detected when present.
* bsps/nand: Update Xilinx NAND driverKinsey Moore2023-01-304-4/+6
| | | | | This resovles gcc warnings by updating to the latest Xilinx NAND controller driver.
* bsps: Add Xilinx GQSPI flash helperAlex White2023-01-271-0/+81
| | | | | | This adds helper functions for working with NOR flash connected to the Xilinx GQSPI controller. The helper functions are based on Xilinx's QSPIPSU flash interrupt example.
* bsps: Import Xilinx GQSPI driverAlex White2023-01-274-0/+2030
| | | | | | | | This adds Xilinx's driver for the Xilinx GQSPI controller embedded in the ZynqMP SoC. Within that device alone, it is possible to access this peripheral from MicroBlaze, ARMv7, and ARMv8 cores. The imported files are and should be able to remain unmodified. Import information is kept in bsps/shared/dev/spi/VERSION.
* tm27: Avoid function pointer castsSebastian Huber2023-01-241-2/+2
| | | | | | | Add TM27_USE_VECTOR_HANDLER to select the interrupt handler type used by the <tm27.h> implementation. Close #4820.
* bsps: Import Xilinx NAND driverKinsey Moore2022-12-234-0/+1560
| | | | | | | | | | This adds Xilinx's driver for the Xilinx NAND controller embedded in the ZynqMP SoC. Within that device alone, it is possible to access this peripheral from MicroBlaze, ARMv7, and ARMv8 cores. This has been added to the hardware ZynqMP BSPs since QEMU does not support emulation of this peripheral. This driver supports polled operation only. The imported files are and should be able to remain unmodified. Import information is kept in bsps/shared/dev/nand/VERSION.
* irq/arm-gicv3.h: Customize CPU Interface initSebastian Huber2022-07-121-21/+37
| | | | | | | Use the existing WRITE_SR() abstraction to access the interrupt group 0 and 1 enable registers. This fixes the build for the AArch32 target. Add BSP options which define the initial values of CPU Interface registers.
* bsps/include: Change license to BSD-2Joel Sherrill2022-07-116-18/+132
| | | | Updates #3053.
* aarch64/gicv3: Remove accesses to secure registersChris Johns2022-06-161-3/+15
| | | | | | RTEMS runs at EL1 and the removed register accesses are for EL3 or the TF-A. This change aligns our driver with the Linux and FreeBSD ones.
* bsps: Add gicv3_get_attributes()Sebastian Huber2022-04-061-0/+32
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* bsps: Add gicv3_sgi_ppi_get_priority()Sebastian Huber2022-04-061-0/+10
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* bsps: Add gicv3_sgi_ppi_set_priority()Sebastian Huber2022-04-061-0/+11
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* bsps: Move gicv3_init_cpu_interface()Sebastian Huber2022-04-061-0/+27
| | | | Make the processor index a parameter.
* bsps: Move gicv3_init_dist()Sebastian Huber2022-04-061-0/+37
| | | | Make the distributor register block a parameter.
* bsps: Add gicv3_sgi_ppi_disable()Sebastian Huber2022-04-061-0/+10
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* bsps: Add gicv3_sgi_ppi_enable()Sebastian Huber2022-04-061-0/+15
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* bsps: Add gicv3_sgi_ppi_is_enabled()Sebastian Huber2022-04-061-0/+10
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* bsps: Add gicv3_ppi_clear_pending()Sebastian Huber2022-04-061-0/+10
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* bsps: Add gicv3_ppi_set_pending()Sebastian Huber2022-04-061-0/+10
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* bsps: Add gicv3_trigger_sgi()Sebastian Huber2022-04-061-0/+21
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* bsps: Add gicv3_sgi_ppi_is_pending()Sebastian Huber2022-04-061-0/+11
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* bsps: Add <dev/irq/arm-gicv3.h>Sebastian Huber2022-04-061-0/+162
| | | | | | | | Separate the Interrupt Manager implementation from the generic Arm GICv3 support. Move parts of the Arm GICv3 support into a new header file. This helps to support systems with a clustered structure in which multiple GICv3 instances are present. For example, two clusters of two Cortex-R52 cores where each cluster has a dedicated GICv3 instance.
* bsps/include/: Scripted embedded brains header file clean upJoel Sherrill2022-03-106-36/+0
| | | | Updates #4625.
* arm/xilinx: Fix zynq-uart interrupt receiveChris Johns2021-09-161-0/+1
| | | | | | | | - Trigger on a single character entering the RX FIFO - Disable the RX timeout - Send up to a FIFO full of data
* bsps/zynq: Moved general i2c files to shared directoriesStephen Clark2021-09-092-0/+134
| | | | | Certain files related to the Zynq BSP's I2C driver are useable by the ZynqMP BSP as well. Moved these files to shared directory in anticipation of I2C support for ZynqMP.
* bsps/irq: Implement new directives for GICv2/3Sebastian Huber2021-07-261-0/+3
| | | | Update #3269.
* bsps/irq: bsp_interrupt_set_affinity()Sebastian Huber2021-07-261-1/+1
| | | | | | Return a status code for bsp_interrupt_set_affinity(). Update #3269.
* bsps/irq: bsp_interrupt_get_affinity()Sebastian Huber2021-07-261-1/+1
| | | | | | Return a status code for bsp_interrupt_get_affinity(). Update #3269.
* bsps/cadence-spi: Fix moduleid offsetKinsey Moore2021-06-291-0/+1
| | | | | Move the moduleid register to the correct offset according to Cadence IP documentation.
* bsps/dev/irq: make icspicfgr an indexable arrayGedare Bloom2021-06-241-4/+2
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