bsps: Import Xilinx NAND driver

This adds Xilinx's driver for the Xilinx NAND controller embedded in the
ZynqMP SoC. Within that device alone, it is possible to access this
peripheral from MicroBlaze, ARMv7, and ARMv8 cores. This has been added
to the hardware ZynqMP BSPs since QEMU does not support emulation of
this peripheral. This driver supports polled operation only. The
imported files are and should be able to remain unmodified. Import
information is kept in bsps/shared/dev/nand/VERSION.

4 files changed, 1560 insertions, 0 deletions

diff --git a/bsps/include/dev/nand/xnandpsu.h b/bsps/include/dev/nand/xnandpsu.h
new file mode 100644
index 0000000000..3625299fb2
--- /dev/null
+++ b/bsps/include/dev/nand/xnandpsu.h
@@ -0,0 +1,581 @@
+/******************************************************************************
+* Copyright (C) 2015 - 2022 Xilinx, Inc.  All rights reserved.
+* SPDX-License-Identifier: MIT
+******************************************************************************/
+
+/*****************************************************************************/
+/**
+*
+* @file xnandpsu.h
+* @addtogroup nandpsu_v1_10
+* @{
+* @details
+*
+* This file implements a driver to support Arasan NAND controller
+* present in Zynq Ultrascale Mp.
+*
+* <b>Driver Initialization</b>
+*
+* The function call XNandPsu_CfgInitialize() should be called by the application
+* before any other function in the driver. The initialization function takes
+* device specific data (like device id, instance id, and base address) and
+* initializes the XNandPsu instance with the device specific data.
+*
+* <b>Device Geometry</b>
+*
+* NAND flash device is memory device and it is segmented into areas called
+* Logical Unit(s) (LUN) and further in to blocks and pages. A NAND flash device
+* can have multiple LUN. LUN is sequential raw of multiple blocks of the same
+* size. A block is the smallest erasable unit of data within the Flash array of
+* a LUN. The size of each block is based on a power of 2. There is no
+* restriction on the number of blocks within the LUN. A block contains a number
+* of pages. A page is the smallest addressable unit for read and program
+* operations. The arrangement of LUN, blocks, and pages is referred to by this
+* module as the part's geometry.
+*
+* The cells within the part can be programmed from a logic 1 to a logic 0
+* and not the other way around. To change a cell back to a logic 1, the
+* entire block containing that cell must be erased. When a block is erased
+* all bytes contain the value 0xFF. The number of times a block can be
+* erased is finite. Eventually the block will wear out and will no longer
+* be capable of erasure. As of this writing, the typical flash block can
+* be erased 100,000 or more times.
+*
+* The jobs done by this driver typically are:
+*	- 8-bit operational mode
+*	- Read, Write, and Erase operation
+*
+* <b>Write Operation</b>
+*
+* The write call can be used to write a minimum of one byte and a maximum
+* entire flash. If the address offset specified to write is out of flash or if
+* the number of bytes specified from the offset exceed flash boundaries
+* an error is reported back to the user. The write is blocking in nature in that
+* the control is returned back to user only after the write operation is
+* completed successfully or an error is reported.
+*
+* <b>Read Operation</b>
+*
+* The read call can be used to read a minimum of one byte and maximum of
+* entire flash. If the address offset specified to read is out of flash or if
+* the number of bytes specified from the offset exceed flash boundaries
+* an error is reported back to the user. The read is blocking in nature in that
+* the control is returned back to user only after the read operation is
+* completed successfully or an error is reported.
+*
+* <b>Erase Operation</b>
+*
+* The erase operations are provided to erase a Block in the Flash memory. The
+* erase call is blocking in nature in that the control is returned back to user
+* only after the erase operation is completed successfully or an error is
+* reported.
+*
+* @note		Driver has been renamed to nandpsu after change in
+*		naming convention.
+*
+* This driver is intended to be RTOS and processor independent. It works with
+* physical addresses only. Any needs for dynamic memory management, threads,
+* mutual exclusion, virtual memory, cache control, or HW write protection
+* management must be satisfied by the layer above this driver.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date	   Changes
+* ----- ----   ----------  -----------------------------------------------
+* 1.0   nm     05/06/2014  First release
+* 2.0   sb     01/12/2015  Removed Null checks for Buffer passed
+*			   as parameter to Read API's
+*			   - XNandPsu_Read()
+*			   - XNandPsu_ReadPage
+*			   Modified
+*			   - XNandPsu_SetFeature()
+*			   - XNandPsu_GetFeature()
+*			   and made them public.
+*			   Removed Failure Return for BCF Error check in
+*			   XNandPsu_ReadPage() and added BCH_Error counter
+*			   in the instance pointer structure.
+* 			   Added XNandPsu_Prepare_Cmd API
+*			   Replaced
+*			   - XNandPsu_IntrStsEnable
+*			   - XNandPsu_IntrStsClear
+*			   - XNandPsu_IntrClear
+*			   - XNandPsu_SetProgramReg
+*			   with XNandPsu_WriteReg call
+*			   Modified xnandpsu.c file API's with above changes.
+* 			   Corrected the program command for Set Feature API.
+*			   Modified
+*			   - XNandPsu_OnfiReadStatus
+*			   - XNandPsu_GetFeature
+*			   - XNandPsu_SetFeature
+*			   to add support for DDR mode.
+*			   Changed Convention for SLC/MLC
+*			   SLC --> HAMMING
+*			   MLC --> BCH
+*			   SlcMlc --> IsBCH
+*			   Added support for writing BBT signature and version
+*			   in page section by enabling XNANDPSU_BBT_NO_OOB.
+*			   Removed extra DMA mode initialization from
+*			   the XNandPsu_CfgInitialize API.
+*			   Modified
+*			   - XNandPsu_SetEccAddrSize
+*			   ECC address now is calculated based upon the
+*			   size of spare area
+*			   Modified Block Erase API, removed clearing of
+*			   packet register before erase.
+*			   Clearing Data Interface Register before
+*			   XNandPsu_OnfiReset call.
+*			   Modified XNandPsu_ChangeTimingMode API supporting
+*			   SDR and NVDDR interface for timing modes 0 to 5.
+*			   Modified Bbt Signature and Version Offset value for
+*			   Oob and No-Oob region.
+* 1.0   kpc    17/06/2015  Increased the timeout for complete event to avoid
+*			   timeout errors for erase operation on slower devices.
+* 1.1   mi     09/16/16 Removed compilation warnings with extra compiler flags.
+* 1.1	nsk    11/07/16    Change memcpy to Xil_MemCpy, CR#960462
+* 1.2   nsk    01/19/17    Fix for the failure of reading nand first redundant
+*                          parameter page. CR#966603
+*       ms     02/12/17    Fix for the compilation warning in _g.c file.
+*       ms     03/17/17    Added readme.txt file in examples folder for doxygen
+*                          generation.
+*       ms     04/10/17    Modified Comment lines in nandpsu_example.c to
+*                          follow doxygen rules.
+* 1.2	nsk    08/08/17    Added support to import example in SDK
+* 1.4	nsk    04/10/18    Added ICCARM compiler support. CR#997552.
+* 1.5   mus    11/08/18    Updated BBT signature array size  in
+*                          XNandPsu_BbtDesc structure to fix the compilation
+*                          warnings.
+# 1.6	sd     06/02/20    Added Clock support
+* 1.6	sd     20/03/20    Added compilation flag
+* 1.8   sg     03/18/21    Added validation check for parameter page.
+* 1.9   akm    07/15/21    Initialize NandInstPtr with Data Interface & Timing mode info.
+* 1.10  akm    10/20/21    Fix gcc warnings.
+* 1.10  akm    12/21/21    Validate input parameters before use.
+* 1.10  akm    01/05/22    Remove assert checks form static and internal APIs.
+*
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XNANDPSU_H		/* prevent circular inclusions */
+#define XNANDPSU_H		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+#include "xil_types.h"
+#include <string.h>
+#include "xstatus.h"
+#include "xil_assert.h"
+#include "xnandpsu_hw.h"
+#include "xnandpsu_onfi.h"
+#include "xil_cache.h"
+#if defined  (XCLOCKING)
+#include "xil_clocking.h"
+#endif
+/************************** Constant Definitions *****************************/
+
+#define XNANDPSU_DEBUG
+
+#define XNANDPSU_MAX_TARGETS		1U	/**< ce_n0, ce_n1 */
+#define XNANDPSU_MAX_PKT_SIZE		0x7FFU	/**< Max packet size */
+#define XNANDPSU_MAX_PKT_COUNT		0xFFFU	/**< Max packet count */
+
+#define XNANDPSU_PAGE_SIZE_512		512U	/**< 512 bytes page */
+#define XNANDPSU_PAGE_SIZE_2K		2048U	/**< 2K bytes page */
+#define XNANDPSU_PAGE_SIZE_4K		4096U	/**< 4K bytes page */
+#define XNANDPSU_PAGE_SIZE_8K		8192U	/**< 8K bytes page */
+#define XNANDPSU_PAGE_SIZE_16K		16384U	/**< 16K bytes page */
+#define XNANDPSU_PAGE_SIZE_1K_16BIT	1024U	/**< 16-bit 2K bytes page */
+#define XNANDPSU_MAX_PAGE_SIZE		16384U	/**< Max page size supported */
+
+#define XNANDPSU_HAMMING		0x1U	/**< Hamming Flash */
+#define XNANDPSU_BCH			0x2U	/**< BCH Flash */
+
+#define XNANDPSU_MAX_BLOCKS		16384U	/**< Max number of Blocks */
+#define XNANDPSU_MAX_SPARE_SIZE		0x800U	/**< Max spare bytes of a NAND
+						  flash page of 16K */
+#define XNANDPSU_MAX_LUNS		8U	/**< Max number of LUNs */
+#define XNANDPSU_MAX_PAGES_PER_BLOCK	512U 	/**< Max number pages per block */
+
+#define XNANDPSU_INTR_POLL_TIMEOUT	0xF000000U
+
+#define XNANDPSU_SDR_CLK		((u16)100U * (u16)1000U * (u16)1000U)
+#define XNANDPSU_NVDDR_CLK_0		((u16)20U * (u16)1000U * (u16)1000U)
+#define XNANDPSU_NVDDR_CLK_1		((u16)33U * (u16)1000U * (u16)1000U)
+#define XNANDPSU_NVDDR_CLK_2		((u16)50U * (u16)1000U * (u16)1000U)
+#define XNANDPSU_NVDDR_CLK_3		((u16)66U * (u16)1000U * (u16)1000U)
+#define XNANDPSU_NVDDR_CLK_4		((u16)83U * (u16)1000U * (u16)1000U)
+#define XNANDPSU_NVDDR_CLK_5		((u16)100U * (u16)1000U * (u16)1000U)
+
+#define XNANDPSU_MAX_TIMING_MODE	5
+/**
+ * The XNandPsu_Config structure contains configuration information for NAND
+ * controller.
+ */
+typedef struct {
+	u16 DeviceId;		/**< Instance ID of NAND flash controller */
+	u32 BaseAddress;	/**< Base address of NAND flash controller */
+	u8 IsCacheCoherent;	/**< Describes whether Cache Coherent or not */
+#if defined  (XCLOCKING)
+	u32 RefClk;		/**< Input clocks */
+#endif
+} XNandPsu_Config;
+
+/**
+ * The XNandPsu_DataInterface enum contains flash operating mode.
+ */
+typedef enum {
+	XNANDPSU_SDR = 0U,		/**< Single Data Rate */
+	XNANDPSU_NVDDR			/**< Double Data Rate */
+} XNandPsu_DataInterface;
+
+/**
+ * XNandPsu_TimingMode enum contains timing modes.
+ */
+typedef enum {
+	XNANDPSU_SDR0 = 0U,
+	XNANDPSU_SDR1,
+	XNANDPSU_SDR2,
+	XNANDPSU_SDR3,
+	XNANDPSU_SDR4,
+	XNANDPSU_SDR5,
+	XNANDPSU_NVDDR0,
+	XNANDPSU_NVDDR1,
+	XNANDPSU_NVDDR2,
+	XNANDPSU_NVDDR3,
+	XNANDPSU_NVDDR4,
+	XNANDPSU_NVDDR5
+} XNandPsu_TimingMode;
+
+/**
+ * The XNandPsu_SWMode enum contains the driver operating mode.
+ */
+typedef enum {
+	XNANDPSU_POLLING = 0,		/**< Polling */
+	XNANDPSU_INTERRUPT		/**< Interrupt */
+} XNandPsu_SWMode;
+
+/**
+ * The XNandPsu_DmaMode enum contains the controller MDMA mode.
+ */
+typedef enum {
+	XNANDPSU_PIO = 0,		/**< PIO Mode */
+	XNANDPSU_SDMA,			/**< SDMA Mode */
+	XNANDPSU_MDMA			/**< MDMA Mode */
+} XNandPsu_DmaMode;
+
+/**
+ * The XNandPsu_EccMode enum contains ECC functionality.
+ */
+typedef enum {
+	XNANDPSU_NONE = 0,
+	XNANDPSU_HWECC,
+	XNANDPSU_EZNAND,
+	XNANDPSU_ONDIE
+} XNandPsu_EccMode;
+
+/**
+ * Bad block table descriptor
+ */
+typedef struct {
+	u32 PageOffset[XNANDPSU_MAX_TARGETS];
+				/**< Page offset where BBT resides */
+	u32 SigOffset;		/**< Signature offset in Spare area */
+	u32 VerOffset;		/**< Offset of BBT version */
+	u32 SigLength;		/**< Length of the signature */
+	u32 MaxBlocks;		/**< Max blocks to search for BBT */
+	char Signature[5];	/**< BBT signature */
+	u8 Version[XNANDPSU_MAX_TARGETS];
+				/**< BBT version */
+	u32 Valid;		/**< BBT descriptor is valid or not */
+} XNandPsu_BbtDesc;
+
+/**
+ * Bad block pattern
+ */
+typedef struct {
+	u32 Options;		/**< Options to search the bad block pattern */
+	u32 Offset;		/**< Offset to search for specified pattern */
+	u32 Length;		/**< Number of bytes to check the pattern */
+	u8 Pattern[2];		/**< Pattern format to search for */
+} XNandPsu_BadBlockPattern;
+
+/**
+ * The XNandPsu_Geometry structure contains the ONFI geometry information.
+ */
+typedef struct {
+	/* Parameter page information */
+	u32 BytesPerPage;	/**< Number of bytes per page */
+	u16 SpareBytesPerPage;	/**< Number of spare bytes per page */
+	u32 PagesPerBlock;	/**< Number of pages per block */
+	u32 BlocksPerLun;	/**< Number of blocks per LUN */
+	u8 NumLuns;		/**< Number of LUN's */
+	u8 RowAddrCycles;	/**< Row address cycles */
+	u8 ColAddrCycles;	/**< Column address cycles */
+	u8 NumBitsPerCell;	/**< Number of bits per cell (Hamming/BCH) */
+	u8 NumBitsECC;		/**< Number of bits ECC correctability */
+	u32 EccCodeWordSize;	/**< ECC codeword size */
+	/* Driver specific information */
+	u32 BlockSize;		/**< Block size */
+	u32 NumTargetPages;	/**< Total number of pages in a Target */
+	u32 NumTargetBlocks;	/**< Total number of blocks in a Target */
+	u64 TargetSize;		/**< Target size in bytes */
+	u8 NumTargets;		/**< Number of targets present */
+	u32 NumPages;		/**< Total number of pages */
+	u32 NumBlocks;		/**< Total number of blocks */
+	u64 DeviceSize;		/**< Total flash size in bytes */
+} XNandPsu_Geometry;
+
+/**
+ * The XNandPsu_Features structure contains the ONFI features information.
+ */
+typedef struct {
+	u32 NvDdr;
+	u32 EzNand;
+	u32 OnDie;
+	u32 ExtPrmPage;
+} XNandPsu_Features;
+
+/**
+ * The XNandPsu_EccMatrix structure contains ECC features information.
+ */
+typedef struct {
+	u16 PageSize;
+	u16 CodeWordSize;
+	u8 NumEccBits;
+	u8 IsBCH;
+	u16 EccAddr;
+	u16 EccSize;
+} XNandPsu_EccMatrix;
+
+/**
+ * The XNandPsu_EccCfg structure contains ECC configuration.
+ */
+typedef struct {
+	u16 EccAddr;
+	u16 EccSize;
+	u16 CodeWordSize;
+	u8 NumEccBits;
+	u8 IsBCH;
+} XNandPsu_EccCfg;
+
+/**
+ * The XNandPsu structure contains the driver instance data. The user is
+ * required to allocate a variable of this type for the NAND controller.
+ * A pointer to a variable of this type is then passed to the driver API
+ * functions.
+ */
+#ifdef __ICCARM__
+#pragma pack(push, 1)
+#endif
+typedef struct {
+	u32 IsReady;		/**< Device is initialized and ready */
+	XNandPsu_Config Config;
+	u32 Ecc_Stat_PerPage_flips;	/**< Ecc Correctable Error Counter for Current Page */
+	u32 Ecc_Stats_total_flips;     /**< Total Ecc Errors Corrected */
+	XNandPsu_DataInterface DataInterface;
+	XNandPsu_TimingMode TimingMode;
+	XNandPsu_SWMode Mode;		/**< Driver operating mode */
+	XNandPsu_DmaMode DmaMode;	/**< MDMA mode enabled/disabled */
+	XNandPsu_EccMode EccMode;	/**< ECC Mode */
+	XNandPsu_EccCfg EccCfg;		/**< ECC configuration */
+	XNandPsu_Geometry Geometry;	/**< Flash geometry */
+	XNandPsu_Features Features;	/**< ONFI features */
+#ifdef __ICCARM__
+	u8 PartialDataBuf[XNANDPSU_MAX_PAGE_SIZE];	/**< Partial read/write buffer */
+#pragma pack(pop)
+#else
+	u8 PartialDataBuf[XNANDPSU_MAX_PAGE_SIZE] __attribute__ ((aligned(64)));
+#endif
+	/* Bad block table definitions */
+	XNandPsu_BbtDesc BbtDesc;	/**< Bad block table descriptor */
+	XNandPsu_BbtDesc BbtMirrorDesc;	/**< Mirror BBT descriptor */
+	XNandPsu_BadBlockPattern BbPattern;	/**< Bad block pattern to
+						  search */
+	u8 Bbt[XNANDPSU_MAX_BLOCKS >> 2];	/**< Bad block table array */
+} XNandPsu;
+
+/******************* Macro Definitions (Inline Functions) *******************/
+
+/*****************************************************************************/
+/**
+ * This macro sets the bitmask in the register.
+ *
+ * @param	InstancePtr is a pointer to the XNandPsu instance of the
+ *		controller.
+ * @param	RegOffset is the register offset.
+ * @param	BitMask is the bitmask.
+ *
+ * @note	C-style signature:
+ *		void XNandPsu_SetBits(XNandPsu *InstancePtr, u32 RegOffset,
+ *							u32 BitMask)
+ *
+ *****************************************************************************/
+#define XNandPsu_SetBits(InstancePtr, RegOffset, BitMask)		\
+	XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,		\
+		(RegOffset),						\
+	((u32)(XNandPsu_ReadReg((InstancePtr)->Config.BaseAddress,	\
+		(RegOffset)) | (BitMask))))
+
+/*****************************************************************************/
+/**
+ * This macro clears the bitmask in the register.
+ *
+ * @param	InstancePtr is a pointer to the XNandPsu instance of the
+ *		controller.
+ * @param	RegOffset is the register offset.
+ * @param	BitMask is the bitmask.
+ *
+ * @note	C-style signature:
+ *		void XNandPsu_ClrBits(XNandPsu *InstancePtr, u32 RegOffset,
+ *							u32 BitMask)
+ *
+ *****************************************************************************/
+#define XNandPsu_ClrBits(InstancePtr, RegOffset, BitMask)		\
+	XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,		\
+		(RegOffset),						\
+	((u32)(XNandPsu_ReadReg((InstancePtr)->Config.BaseAddress,	\
+		(RegOffset)) & ~(BitMask))))
+
+/*****************************************************************************/
+/**
+ * This macro clears and updates the bitmask in the register.
+ *
+ * @param	InstancePtr is a pointer to the XNandPsu instance of the
+ *		controller.
+ * @param	RegOffset is the register offset.
+ * @param	Mask is the bitmask.
+ * @param	Value is the register value to write.
+ *
+ * @note	C-style signature:
+ *		void XNandPsu_ReadModifyWrite(XNandPsu *InstancePtr,
+ *					u32 RegOffset, u32 Mask, u32 Val)
+ *
+ *****************************************************************************/
+#define XNandPsu_ReadModifyWrite(InstancePtr, RegOffset, Mask, Value)	\
+	XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,		\
+		(RegOffset),						\
+	((u32)((u32)(XNandPsu_ReadReg((InstancePtr)->Config.BaseAddress,\
+		(u32)(RegOffset)) & (u32)(~(Mask))) | (u32)(Value))))
+
+/*****************************************************************************/
+/**
+ * This macro enables bitmask in Interrupt Signal Enable register.
+ *
+ * @param	InstancePtr is a pointer to the XNandPsu instance of the
+ *		controller.
+ * @param	Mask is the bitmask.
+ *
+ * @note	C-style signature:
+ *		void XNandPsu_IntrSigEnable(XNandPsu *InstancePtr, u32 Mask)
+ *
+ *****************************************************************************/
+#define XNandPsu_IntrSigEnable(InstancePtr, Mask)			\
+		XNandPsu_SetBits((InstancePtr),				\
+			XNANDPSU_INTR_SIG_EN_OFFSET,			\
+			(Mask))
+
+/*****************************************************************************/
+/**
+ * This macro clears bitmask in Interrupt Signal Enable register.
+ *
+ * @param	InstancePtr is a pointer to the XNandPsu instance of the
+ *		controller.
+ * @param	Mask is the bitmask.
+ *
+ * @note	C-style signature:
+ *		void XNandPsu_IntrSigClear(XNandPsu *InstancePtr, u32 Mask)
+ *
+ *****************************************************************************/
+#define XNandPsu_IntrSigClear(InstancePtr, Mask)			\
+		XNandPsu_ClrBits((InstancePtr),				\
+			XNANDPSU_INTR_SIG_EN_OFFSET,			\
+			(Mask))
+
+/*****************************************************************************/
+/**
+ * This macro enables bitmask in Interrupt Status Enable register.
+ *
+ * @param	InstancePtr is a pointer to the XNandPsu instance of the
+ *		controller.
+ * @param	Mask is the bitmask.
+ *
+ * @note	C-style signature:
+ *		void XNandPsu_IntrStsEnable(XNandPsu *InstancePtr, u32 Mask)
+ *
+ *****************************************************************************/
+#define XNandPsu_IntrStsEnable(InstancePtr, Mask)			\
+		XNandPsu_SetBits((InstancePtr),				\
+			XNANDPSU_INTR_STS_EN_OFFSET,			\
+			(Mask))
+
+/*****************************************************************************/
+/**
+ * This macro checks for the ONFI ID.
+ *
+ * @param	Buff is the buffer holding ONFI ID
+ *
+ * @note	none.
+ *
+ *****************************************************************************/
+#define IS_ONFI(Buff)					\
+	((Buff)[0] == (u8)'O') && ((Buff)[1] == (u8)'N') &&	\
+	((Buff)[2] == (u8)'F') && ((Buff)[3] == (u8)'I')
+
+/************************** Function Prototypes *****************************/
+
+s32 XNandPsu_CfgInitialize(XNandPsu *InstancePtr, XNandPsu_Config *ConfigPtr,
+				u32 EffectiveAddr);
+
+s32 XNandPsu_Erase(XNandPsu *InstancePtr, u64 Offset, u64 Length);
+
+s32 XNandPsu_Write(XNandPsu *InstancePtr, u64 Offset, u64 Length,
+							u8 *SrcBuf);
+
+s32 XNandPsu_Read(XNandPsu *InstancePtr, u64 Offset, u64 Length,
+							u8 *DestBuf);
+
+s32 XNandPsu_EraseBlock(XNandPsu *InstancePtr, u32 Target, u32 Block);
+
+s32 XNandPsu_WriteSpareBytes(XNandPsu *InstancePtr, u32 Page, u8 *Buf);
+
+s32 XNandPsu_ReadSpareBytes(XNandPsu *InstancePtr, u32 Page, u8 *Buf);
+
+s32 XNandPsu_ChangeTimingMode(XNandPsu *InstancePtr,
+				XNandPsu_DataInterface NewIntf,
+				XNandPsu_TimingMode NewMode);
+
+s32 XNandPsu_GetFeature(XNandPsu *InstancePtr, u32 Target, u8 Feature,
+								u8 *Buf);
+
+s32 XNandPsu_SetFeature(XNandPsu *InstancePtr, u32 Target, u8 Feature,
+								u8 *Buf);
+
+s32 XNandPsu_ScanBbt(XNandPsu *InstancePtr);
+
+s32 XNandPsu_MarkBlockBad(XNandPsu *InstancePtr, u32 Block);
+
+void XNandPsu_EnableDmaMode(XNandPsu *InstancePtr);
+
+void XNandPsu_DisableDmaMode(XNandPsu *InstancePtr);
+
+void XNandPsu_EnableEccMode(XNandPsu *InstancePtr);
+
+void XNandPsu_DisableEccMode(XNandPsu *InstancePtr);
+
+void XNandPsu_Prepare_Cmd(XNandPsu *InstancePtr, u8 Cmd1, u8 Cmd2, u8 EccState,
+			u8 DmaMode, u8 AddrCycles);
+
+/* XNandPsu_LookupConfig in xnandpsu_sinit.c */
+XNandPsu_Config *XNandPsu_LookupConfig(u16 DevID);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* XNANDPSU_H end of protection macro */
+/** @} */
diff --git a/bsps/include/dev/nand/xnandpsu_bbm.h b/bsps/include/dev/nand/xnandpsu_bbm.h
new file mode 100644
index 0000000000..4d4fafffa3
--- /dev/null
+++ b/bsps/include/dev/nand/xnandpsu_bbm.h
@@ -0,0 +1,180 @@
+/******************************************************************************
+* Copyright (C) 2015 - 2022 Xilinx, Inc.  All rights reserved.
+* SPDX-License-Identifier: MIT
+******************************************************************************/
+
+/*****************************************************************************/
+/**
+*
+* @file xnandpsu_bbm.h
+* @addtogroup nandpsu_v1_10
+* @{
+*
+* This file implements the Bad Block Management(BBM) functionality. This is
+* similar to the Bad Block Management which is a part of the MTD subsystem in
+* Linux.  The factory marked bad blocks are scanned initially and a Bad Block
+* Table(BBT) is created in the memory.  This table is also written to the flash
+* so that upon reboot, the BBT is read back from the flash and loaded into the
+* memory instead of scanning every time. The Bad Block Table(BBT) is written
+* into one of the the last four blocks in the flash memory. The last four
+* blocks are marked as Reserved so that user can't erase/program those blocks.
+*
+* There are two bad block tables, a primary table and a mirror table. The
+* tables are versioned and incrementing version number is used to detect and
+* recover from interrupted updates. Each table is stored in a separate block,
+* beginning in the first page of that block. Only two blocks would be necessary
+* in the absence of bad blocks within the last four; the range of four provides
+* a little slack in case one or two of those blocks is bad. These blocks are
+* marked as reserved and cannot be programmed by the user. A NAND Flash device
+* with 3 or more factory bad blocks in the last 4 cannot be used. The bad block
+* table signature is written into the spare data area of the pages containing
+* bad block table so that upon rebooting the bad block table signature is
+* searched and the bad block table is loaded into RAM. The signature is "Bbt0"
+* for primary Bad Block Table and "1tbB" for Mirror Bad Block Table. The
+* version offset follows the signature offset in the spare data area. The
+* version number increments on every update to the bad block table and the
+* version wraps at 0xff.
+*
+* Each block in the Bad Block Table(BBT) is represented by 2 bits.
+* The two bits are encoded as follows in RAM BBT.
+* 0'b00 -> Good Block
+* 0'b01 -> Block is bad due to wear
+* 0'b10 -> Reserved block
+* 0'b11 -> Factory marked bad block
+*
+* While writing to the flash the two bits are encoded as follows.
+* 0'b00 -> Factory marked bad block
+* 0'b01 -> Reserved block
+* 0'b10 -> Block is bad due to wear
+* 0'b11 -> Good Block
+*
+* The user can check for the validity of the block using the API
+* XNandPsu_IsBlockBad and take the action based on the return value. Also user
+* can update the bad block table using XNandPsu_MarkBlockBad API.
+*
+* @note		None
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date        Changes
+* ----- ----   ----------  -----------------------------------------------
+* 1.0   nm     05/06/2014  First release
+* 2.0   sb     01/12/2015  Added support for writing BBT signature and version
+*			   in page section by enabling XNANDPSU_BBT_NO_OOB.
+*			   Modified Bbt Signature and Version Offset value for
+*			   Oob and No-Oob region.
+* </pre>
+*
+******************************************************************************/
+#ifndef XNANDPSU_BBM_H		/* prevent circular inclusions */
+#define XNANDPSU_BBM_H		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+#include "xnandpsu.h"
+
+/************************** Constant Definitions *****************************/
+/* Block definitions for RAM based Bad Block Table (BBT) */
+#define XNANDPSU_BLOCK_GOOD			0x0U	/**< Block is good */
+#define XNANDPSU_BLOCK_BAD			0x1U	/**< Block is bad */
+#define XNANDPSU_BLOCK_RESERVED			0x2U	/**< Reserved block */
+#define XNANDPSU_BLOCK_FACTORY_BAD		0x3U	/**< Factory marked bad
+							  block */
+/* Block definitions for FLASH based Bad Block Table (BBT) */
+#define XNANDPSU_FLASH_BLOCK_GOOD		0x3U	/**< Block is good */
+#define XNANDPSU_FLASH_BLOCK_BAD		0x2U	/**< Block is bad */
+#define XNANDPSU_FLASH_BLOCK_RESERVED		0x1U	/**< Reserved block */
+#define XNANDPSU_FLASH_BLOCK_FAC_BAD	0x0U	/**< Factory marked bad
+							  block */
+
+#define XNANDPSU_BBT_SCAN_2ND_PAGE		0x00000001U	/**< Scan the
+								  second page
+								  for bad block
+								  information
+								  */
+#define XNANDPSU_BBT_DESC_PAGE_OFFSET		0U	/**< Page offset of Bad
+							  Block Table Desc */
+#define XNANDPSU_BBT_DESC_SIG_OFFSET		8U	/**< Bad Block Table
+							  signature offset */
+#define XNANDPSU_BBT_DESC_VER_OFFSET		12U	/**< Bad block Table
+							  version offset */
+#define XNANDPSU_NO_OOB_BBT_DESC_SIG_OFFSET	0U	/**< Bad Block Table
+							  signature offset in
+							  page memory */
+#define XNANDPSU_NO_OOB_BBT_DESC_VER_OFFSET	4U	/**< Bad block Table
+							  version offset in
+							  page memory */
+#define XNANDPSU_BBT_DESC_SIG_LEN		4U	/**< Bad block Table
+							  signature length */
+#define XNANDPSU_BBT_DESC_MAX_BLOCKS		64U	/**< Bad block Table
+							  max blocks */
+
+#define XNANDPSU_BBT_BLOCK_SHIFT		2U	/**< Block shift value
+							  for a block in BBT */
+#define XNANDPSU_BBT_ENTRY_NUM_BLOCKS		4U	/**< Num of blocks in
+							  one BBT entry */
+#define XNANDPSU_BB_PTRN_OFF_SML_PAGE	5U	/**< Bad block pattern
+							  offset in a page */
+#define XNANDPSU_BB_PTRN_LEN_SML_PAGE	1U	/**< Bad block pattern
+							  length */
+#define XNANDPSU_BB_PTRN_OFF_LARGE_PAGE	0U	/**< Bad block pattern
+							  offset in a large
+							  page */
+#define XNANDPSU_BB_PTRN_LEN_LARGE_PAGE	2U	/**< Bad block pattern
+							  length */
+#define XNANDPSU_BB_PATTERN			0xFFU	/**< Bad block pattern
+							  to search in a page
+							  */
+#define XNANDPSU_BLOCK_TYPE_MASK		0x03U	/**< Block type mask */
+#define XNANDPSU_BLOCK_SHIFT_MASK		0x06U	/**< Block shift mask
+							  for a Bad Block Table
+							  entry byte */
+
+#define XNANDPSU_ONDIE_SIG_OFFSET		0x4U
+#define XNANDPSU_ONDIE_VER_OFFSET		0x14U
+
+#define XNANDPSU_BBT_VERSION_LENGTH	1U
+#define XNANDPSU_BBT_SIG_LENGTH		4U
+
+#define XNANDPSU_BBT_BUF_LENGTH		((XNANDPSU_MAX_BLOCKS >> 		\
+					 XNANDPSU_BBT_BLOCK_SHIFT) +	\
+					(XNANDPSU_BBT_DESC_SIG_OFFSET +	\
+					 XNANDPSU_BBT_SIG_LENGTH +	\
+					 XNANDPSU_BBT_VERSION_LENGTH))
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+*
+* This macro returns the Block shift value corresponding to a Block.
+*
+* @param        Block is the block number.
+*
+* @return       Block shift value
+*
+* @note         None.
+*
+*****************************************************************************/
+#define XNandPsu_BbtBlockShift(Block) \
+			(u8)(((Block) * 2U) & XNANDPSU_BLOCK_SHIFT_MASK)
+
+/************************** Variable Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+
+void XNandPsu_InitBbtDesc(XNandPsu *InstancePtr);
+
+s32 XNandPsu_IsBlockBad(XNandPsu *InstancePtr, u32 Block);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/bsps/include/dev/nand/xnandpsu_hw.h b/bsps/include/dev/nand/xnandpsu_hw.h
new file mode 100644
index 0000000000..47e6c8fddc
--- /dev/null
+++ b/bsps/include/dev/nand/xnandpsu_hw.h
@@ -0,0 +1,483 @@
+/******************************************************************************
+* Copyright (C) 2015 - 2022 Xilinx, Inc.  All rights reserved.
+* SPDX-License-Identifier: MIT
+******************************************************************************/
+
+/*****************************************************************************/
+/**
+*
+* @file xnandpsu_hw.h
+* @addtogroup nandpsu_v1_10
+* @{
+*
+* This file contains identifiers and low-level macros/functions for the Arasan
+* NAND flash controller driver.
+*
+* See xnandpsu.h for more information.
+*
+* @note		None
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date        Changes
+* ----- ----   ----------  -----------------------------------------------
+* 1.0   nm     05/06/2014  First Release
+* 2.0   sb     11/04/2014  Changed XNANDPSU_ECC_SLC_MLC_MASK to
+*			   XNANDPSU_ECC_HAMMING_BCH_MASK.
+* 1.7	akm    09/03/20    Updated the Makefile to support parallel make
+* 			   execution.
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XNANDPSU_HW_H		/* prevent circular inclusions */
+#define XNANDPSU_HW_H		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+#include "xil_io.h"
+
+/************************** Constant Definitions *****************************/
+
+/************************** Register Offset Definitions **********************/
+
+#define XNANDPSU_PKT_OFFSET		0x00U	/**< Packet Register */
+#define XNANDPSU_MEM_ADDR1_OFFSET	0x04U	/**< Memory Address
+						  Register 1 */
+#define XNANDPSU_MEM_ADDR2_OFFSET	0x08U	/**< Memory Address
+						  Register 2 */
+#define XNANDPSU_CMD_OFFSET		0x0CU	/**< Command Register */
+#define XNANDPSU_PROG_OFFSET		0x10U	/**< Program Register */
+#define XNANDPSU_INTR_STS_EN_OFFSET	0x14U	/**< Interrupt Status
+						     Enable Register */
+#define XNANDPSU_INTR_SIG_EN_OFFSET	0x18U	/**< Interrupt Signal
+						     Enable Register */
+#define XNANDPSU_INTR_STS_OFFSET	0x1CU	/**< Interrupt Status
+						  Register */
+#define XNANDPSU_READY_BUSY_OFFSET	0x20U	/**< Ready/Busy status
+						  Register */
+#define XNANDPSU_FLASH_STS_OFFSET	0x28U	/**< Flash Status Register */
+#define XNANDPSU_TIMING_OFFSET		0x2CU	/**< Timing Register */
+#define XNANDPSU_BUF_DATA_PORT_OFFSET	0x30U	/**< Buffer Data Port
+						  Register */
+#define XNANDPSU_ECC_OFFSET		0x34U	/**< ECC Register */
+#define XNANDPSU_ECC_ERR_CNT_OFFSET	0x38U	/**< ECC Error Count
+						  Register */
+#define XNANDPSU_ECC_SPR_CMD_OFFSET	0x3CU	/**< ECC Spare Command
+						     Register */
+#define XNANDPSU_ECC_CNT_1BIT_OFFSET	0x40U	/**< Error Count 1bit
+						  Register */
+#define XNANDPSU_ECC_CNT_2BIT_OFFSET	0x44U	/**< Error Count 2bit
+						  Register */
+#define XNANDPSU_ECC_CNT_3BIT_OFFSET	0x48U	/**< Error Count 3bit
+						  Register */
+#define XNANDPSU_ECC_CNT_4BIT_OFFSET	0x4CU	/**< Error Count 4bit
+						  Register */
+#define XNANDPSU_CPU_REL_OFFSET		0x58U	/**< CPU Release Register */
+#define XNANDPSU_ECC_CNT_5BIT_OFFSET	0x5CU	/**< Error Count 5bit
+						  Register */
+#define XNANDPSU_ECC_CNT_6BIT_OFFSET	0x60U	/**< Error Count 6bit
+						  Register */
+#define XNANDPSU_ECC_CNT_7BIT_OFFSET	0x64U	/**< Error Count 7bit
+						  Register */
+#define XNANDPSU_ECC_CNT_8BIT_OFFSET	0x68U	/**< Error Count 8bit
+						  Register */
+#define XNANDPSU_DATA_INTF_OFFSET	0x6CU	/**< Data Interface Register */
+#define XNANDPSU_DMA_SYS_ADDR0_OFFSET	0x50U	/**< DMA System Address 0
+						  Register */
+#define XNANDPSU_DMA_SYS_ADDR1_OFFSET	0x24U	/**< DMA System Address 1
+						  Register */
+#define XNANDPSU_DMA_BUF_BND_OFFSET	0x54U	/**< DMA Buffer Boundary
+						  Register */
+#define XNANDPSU_SLV_DMA_CONF_OFFSET	0x80U	/**< Slave DMA Configuration
+						  Register */
+
+/** @name Packet Register bit definitions and masks
+ *  @{
+ */
+#define XNANDPSU_PKT_PKT_SIZE_MASK		0x000007FFU /**< Packet Size */
+#define XNANDPSU_PKT_PKT_CNT_MASK		0x00FFF000U /**< Packet Count*/
+#define XNANDPSU_PKT_PKT_CNT_SHIFT		12U /**< Packet Count Shift */
+/* @} */
+
+/** @name Memory Address Register 1 bit definitions and masks
+ *  @{
+ */
+#define XNANDPSU_MEM_ADDR1_COL_ADDR_MASK	0x0000FFFFU /**< Column Address
+							     Mask */
+#define XNANDPSU_MEM_ADDR1_PG_ADDR_MASK		0xFFFF0000U /**< Page, Block
+							     Address Mask */
+#define XNANDPSU_MEM_ADDR1_PG_ADDR_SHIFT	16U /**< Page Shift */
+/* @} */
+
+/** @name Memory Address Register 2 bit definitions and masks
+ *  @{
+ */
+#define XNANDPSU_MEM_ADDR2_MEM_ADDR_MASK	0x000000FFU /**< Memory Address
+								*/
+#define XNANDPSU_MEM_ADDR2_BUS_WIDTH_MASK	0x01000000U /**< Bus Width */
+#define XNANDPSU_MEM_ADDR2_NFC_BCH_MODE_MASK	0x0E000000U /**< BCH Mode
+							     Value */
+#define XNANDPSU_MEM_ADDR2_MODE_MASK		0x30000000U /**< Flash
+							     Connection Mode */
+#define XNANDPSU_MEM_ADDR2_CHIP_SEL_MASK	0xC0000000U /**< Chip Select */
+#define XNANDPSU_MEM_ADDR2_CHIP_SEL_SHIFT	30U	/**< Chip select
+							shift */
+#define XNANDPSU_MEM_ADDR2_BUS_WIDTH_SHIFT	24U	/**< Bus width shift */
+#define XNANDPSU_MEM_ADDR2_NFC_BCH_MODE_SHIFT	25U
+/* @} */
+
+/** @name Command Register bit definitions and masks
+ *  @{
+ */
+#define XNANDPSU_CMD_CMD1_MASK			0x000000FFU /**< 1st Cycle
+							     Command */
+#define XNANDPSU_CMD_CMD2_MASK			0x0000FF00U /**< 2nd Cycle
+							     Command */
+#define XNANDPSU_CMD_PG_SIZE_MASK		0x03800000U /**< Page Size */
+#define XNANDPSU_CMD_DMA_EN_MASK		0x0C000000U /**< DMA Enable
+							     Mode */
+#define XNANDPSU_CMD_ADDR_CYCLES_MASK		0x70000000U /**< Number of
+							     Address Cycles */
+#define XNANDPSU_CMD_ECC_ON_MASK		0x80000000U /**< ECC ON/OFF */
+#define XNANDPSU_CMD_CMD2_SHIFT			8U /**< 2nd Cycle Command
+						    Shift */
+#define XNANDPSU_CMD_PG_SIZE_SHIFT		23U /**< Page Size Shift */
+#define XNANDPSU_CMD_DMA_EN_SHIFT		26U /**< DMA Enable Shift */
+#define XNANDPSU_CMD_ADDR_CYCLES_SHIFT		28U /**< Number of Address
+						     Cycles Shift */
+#define XNANDPSU_CMD_ECC_ON_SHIFT		31U /**< ECC ON/OFF */
+/* @} */
+
+/** @name Program Register bit definitions and masks
+ *  @{
+ */
+#define XNANDPSU_PROG_RD_MASK			0x00000001U /**< Read */
+#define XNANDPSU_PROG_MUL_DIE_MASK		0x00000002U /**< Multi Die */
+#define XNANDPSU_PROG_BLK_ERASE_MASK		0x00000004U /**< Block Erase */
+#define XNANDPSU_PROG_RD_STS_MASK		0x00000008U /**< Read Status */
+#define XNANDPSU_PROG_PG_PROG_MASK		0x00000010U /**< Page Program */
+#define XNANDPSU_PROG_MUL_DIE_RD_MASK		0x00000020U /**< Multi Die Rd */
+#define XNANDPSU_PROG_RD_ID_MASK		0x00000040U /**< Read ID */
+#define XNANDPSU_PROG_RD_PRM_PG_MASK		0x00000080U /**< Read Param
+							     Page */
+#define XNANDPSU_PROG_RST_MASK			0x00000100U /**< Reset */
+#define XNANDPSU_PROG_GET_FEATURES_MASK		0x00000200U /**< Get Features */
+#define XNANDPSU_PROG_SET_FEATURES_MASK		0x00000400U /**< Set Features */
+#define XNANDPSU_PROG_RD_UNQ_ID_MASK		0x00000800U /**< Read Unique
+							     ID */
+#define XNANDPSU_PROG_RD_STS_ENH_MASK		0x00001000U /**< Read Status
+							     Enhanced */
+#define XNANDPSU_PROG_RD_INTRLVD_MASK		0x00002000U /**< Read
+							     Interleaved */
+#define XNANDPSU_PROG_CHNG_RD_COL_ENH_MASK	0x00004000U /**< Change Read
+								Column
+								Enhanced */
+#define XNANDPSU_PROG_COPY_BACK_INTRLVD_MASK	0x00008000U /**< Copy Back
+								Interleaved */
+#define XNANDPSU_PROG_RD_CACHE_START_MASK	0x00010000U /**< Read Cache
+							     Start */
+#define XNANDPSU_PROG_RD_CACHE_SEQ_MASK		0x00020000U /**< Read Cache
+							     Sequential */
+#define XNANDPSU_PROG_RD_CACHE_RAND_MASK	0x00040000U /**< Read Cache
+								Random */
+#define XNANDPSU_PROG_RD_CACHE_END_MASK		0x00080000U /**< Read Cache
+							     End */
+#define XNANDPSU_PROG_SMALL_DATA_MOVE_MASK	0x00100000U /**< Small Data
+							     Move */
+#define XNANDPSU_PROG_CHNG_ROW_ADDR_MASK	0x00200000U /**< Change Row
+								Address */
+#define XNANDPSU_PROG_CHNG_ROW_ADDR_END_MASK	0x00400000U /**< Change Row
+								Address End */
+#define XNANDPSU_PROG_RST_LUN_MASK		0x00800000U /**< Reset LUN */
+#define XNANDPSU_PROG_PGM_PG_CLR_MASK		0x01000000U /**< Enhanced
+							     Program Page
+							     Register Clear */
+#define XNANDPSU_PROG_VOL_SEL_MASK		0x02000000U /**< Volume Select */
+#define XNANDPSU_PROG_ODT_CONF_MASK		0x04000000U /**< ODT Configure */
+/* @} */
+
+/** @name Interrupt Status Enable Register bit definitions and masks
+ *  @{
+ */
+#define XNANDPSU_INTR_STS_EN_BUFF_WR_RDY_STS_EN_MASK	0x00000001U /**< Buffer
+								     Write Ready
+								     Status
+								     Enable */
+#define XNANDPSU_INTR_STS_EN_BUFF_RD_RDY_STS_EN_MASK	0x00000002U /**< Buffer
+								     Read Ready
+								     Status
+								     Enable */
+#define XNANDPSU_INTR_STS_EN_TRANS_COMP_STS_EN_MASK	0x00000004U /**< Transfer
+								     Complete
+								     Status
+								     Enable */
+#define XNANDPSU_INTR_STS_EN_MUL_BIT_ERR_STS_EN_MASK	0x00000008U /**< Multi
+								     Bit Error
+								     Status
+								     Enable */
+#define XNANDPSU_INTR_STS_EN_ERR_INTR_STS_EN_MASK	0x00000010U /**< Single
+								     Bit Error
+								     Status
+								     Enable,
+								     BCH Detect
+								     Error
+								     Status
+								     Enable */
+#define XNANDPSU_INTR_STS_EN_DMA_INT_STS_EN_MASK	0x00000040U /**< DMA
+								     Status
+								     Enable */
+#define XNANDPSU_INTR_STS_EN_ERR_AHB_STS_EN_MASK	0x00000080U /**< Error
+								     AHB Status
+								     Enable */
+/* @} */
+
+/** @name Interrupt Signal Enable Register bit definitions and masks
+ *  @{
+ */
+#define XNANDPSU_INTR_SIG_EN_BUFF_WR_RDY_STS_EN_MASK	0x00000001U /**< Buffer
+								     Write Ready
+								     Signal
+								     Enable */
+#define XNANDPSU_INTR_SIG_EN_BUFF_RD_RDY_STS_EN_MASK	0x00000002U /**< Buffer
+								     Read Ready
+								     Signal
+								     Enable */
+#define XNANDPSU_INTR_SIG_EN_TRANS_COMP_STS_EN_MASK	0x00000004U /**< Transfer
+								     Complete
+								     Signal
+								     Enable */
+#define XNANDPSU_INTR_SIG_EN_MUL_BIT_ERR_STS_EN_MASK	0x00000008U /**< Multi
+								     Bit Error
+								     Signal
+								     Enable */
+#define XNANDPSU_INTR_SIG_EN_ERR_INTR_STS_EN_MASK	0x00000010U /**< Single
+								     Bit Error
+								     Signal
+								     Enable,
+								     BCH Detect
+								     Error
+								     Signal
+								     Enable */
+#define XNANDPSU_INTR_SIG_EN_DMA_INT_STS_EN_MASK	0x00000040U /**< DMA
+								     Signal
+								     Enable */
+#define XNANDPSU_INTR_SIG_EN_ERR_AHB_STS_EN_MASK	0x00000080U /**< Error
+								     AHB Signal
+								     Enable */
+/* @} */
+
+/** @name Interrupt Status Register bit definitions and masks
+ *  @{
+ */
+#define XNANDPSU_INTR_STS_BUFF_WR_RDY_STS_EN_MASK	0x00000001U /**< Buffer
+								     Write
+								     Ready */
+#define XNANDPSU_INTR_STS_BUFF_RD_RDY_STS_EN_MASK	0x00000002U /**< Buffer
+								     Read
+								     Ready */
+#define XNANDPSU_INTR_STS_TRANS_COMP_STS_EN_MASK	0x00000004U /**< Transfer
+								     Complete */
+#define XNANDPSU_INTR_STS_MUL_BIT_ERR_STS_EN_MASK	0x00000008U /**< Multi
+								    Bit Error */
+#define XNANDPSU_INTR_STS_ERR_INTR_STS_EN_MASK		0x00000010U /**< Single
+								     Bit Error,
+								     BCH Detect
+								     Error */
+#define XNANDPSU_INTR_STS_DMA_INT_STS_EN_MASK		0x00000040U /**< DMA
+								     Interrupt
+								     */
+#define XNANDPSU_INTR_STS_ERR_AHB_STS_EN_MASK		0x00000080U /**< Error
+								     AHB */
+/* @} */
+
+/** @name Interrupt bit definitions and masks
+ *  @{
+ */
+#define XNANDPSU_INTR_BUFF_WR_RDY_STS_EN_MASK	0x00000001U /**< Buffer Write
+								Ready Status
+								Enable */
+#define XNANDPSU_INTR_BUFF_RD_RDY_STS_EN_MASK	0x00000002U /**< Buffer Read
+								Ready Status
+								Enable */
+#define XNANDPSU_INTR_TRANS_COMP_STS_EN_MASK	0x00000004U /**< Transfer
+								Complete Status
+								Enable */
+#define XNANDPSU_INTR_MUL_BIT_ERR_STS_EN_MASK	0x00000008U /**< Multi Bit Error
+								Status Enable */
+#define XNANDPSU_INTR_ERR_INTR_STS_EN_MASK	0x00000010U /**< Single Bit Error
+								Status Enable,
+								BCH Detect Error
+								Status Enable */
+#define XNANDPSU_INTR_DMA_INT_STS_EN_MASK	0x00000040U /**< DMA Status
+								Enable */
+#define XNANDPSU_INTR_ERR_AHB_STS_EN_MASK	0x00000080U /**< Error AHB Status
+								Enable */
+/* @} */
+
+/** @name ID2 Register bit definitions and masks
+ *  @{
+ */
+#define XNANDPSU_ID2_DEVICE_ID2_MASK		0x000000FFU /**< MSB Device ID */
+/* @} */
+
+/** @name Flash Status Register bit definitions and masks
+ *  @{
+ */
+#define XNANDPSU_FLASH_STS_FLASH_STS_MASK	0x0000FFFFU /**< Flash Status
+							     Value */
+/* @} */
+
+/** @name Timing Register bit definitions and masks
+ *  @{
+ */
+#define XNANDPSU_TIMING_TCCS_TIME_MASK		0x00000003U /**< Change column
+							     setup time */
+#define XNANDPSU_TIMING_SLOW_FAST_TCAD_MASK	0x00000004U /**< Slow/Fast device
+							     */
+#define XNANDPSU_TIMING_DQS_BUFF_SEL_MASK	0x00000078U /**< Write/Read data
+							     transaction value
+							     */
+#define XNANDPSU_TIMING_TADL_TIME_MASK		0x00007F80U /**< Address latch
+							     enable to Data
+							     loading time */
+/* @} */
+
+/** @name ECC Register bit definitions and masks
+ *  @{
+ */
+#define XNANDPSU_ECC_ADDR_MASK			0x0000FFFFU /**< ECC address */
+#define XNANDPSU_ECC_SIZE_MASK			0x01FF0000U /**< ECC size */
+#define XNANDPSU_ECC_HAMMING_BCH_MASK		0x02000000U /**< Hamming/BCH
+							     support */
+/* @} */
+
+/** @name ECC Error Count Register bit definitions and masks
+ *  @{
+ */
+#define XNANDPSU_ECC_ERR_CNT_PKT_BND_ERR_CNT_MASK	0x000000FFU /**< Packet
+								     bound error
+								     count */
+#define XNANDPSU_ECC_ERR_CNT_PG_BND_ERR_CNT_MASK	0x0000FF00U /**< Page
+								     bound error
+								     count */
+/* @} */
+
+/** @name ECC Spare Command Register bit definitions and masks
+ *  @{
+ */
+#define XNANDPSU_ECC_SPR_CMD_SPR_CMD_MASK		0x000000FFU /**< ECC
+								     spare
+								     command */
+#define XNANDPSU_ECC_SPR_CMD_ECC_ADDR_CYCLES_MASK	0x70000000U /**< Number
+								     of ECC/
+								     spare
+								     address
+								     cycles */
+/* @} */
+
+/** @name Data Interface Register bit definitions and masks
+ *  @{
+ */
+#define XNANDPSU_DATA_INTF_SDR_MASK		0x00000007U /**< SDR mode */
+#define XNANDPSU_DATA_INTF_NVDDR_MASK		0x00000038U /**< NVDDR mode */
+#define XNANDPSU_DATA_INTF_NVDDR2_MASK		0x000001C0U /**< NVDDR2 mode */
+#define XNANDPSU_DATA_INTF_DATA_INTF_MASK	0x00000600U /**< Data
+							     Interface */
+#define XNANDPSU_DATA_INTF_NVDDR_SHIFT		3U /**< NVDDR mode shift */
+#define XNANDPSU_DATA_INTF_DATA_INTF_SHIFT	9U /**< Data Interface Shift */
+/* @} */
+
+/** @name DMA Buffer Boundary Register bit definitions and masks
+ *  @{
+ */
+#define XNANDPSU_DMA_BUF_BND_BND_MASK		0x00000007U /**< DMA buffer
+							     boundary */
+#define XNANDPSU_DMA_BUF_BND_4K			0x0U
+#define XNANDPSU_DMA_BUF_BND_8K			0x1U
+#define XNANDPSU_DMA_BUF_BND_16K		0x2U
+#define XNANDPSU_DMA_BUF_BND_32K		0x3U
+#define XNANDPSU_DMA_BUF_BND_64K		0x4U
+#define XNANDPSU_DMA_BUF_BND_128K		0x5U
+#define XNANDPSU_DMA_BUF_BND_256K		0x6U
+#define XNANDPSU_DMA_BUF_BND_512K		0x7U
+/* @} */
+
+/** @name Slave DMA Configuration Register bit definitions and masks
+ *  @{
+ */
+#define XNANDPSU_SLV_DMA_CONF_SDMA_TX_RX_MASK		0x00000001U /**< Slave
+								     DMA
+								     Transfer
+								     Direction
+								     */
+#define XNANDPSU_SLV_DMA_CONF_DMA_TRANS_CNT_MASK	0x001FFFFEU /**< Slave
+								     DMA
+								     Transfer
+								     Count */
+#define XNANDPSU_SLV_DMA_CONF_DMA_BURST_SIZE_MASK	0x00E00000U /**< Slave
+								     DMA
+								     Burst
+								     Size */
+#define XNANDPSU_SLV_DMA_CONF_DMA_TMOUT_CNT_VAL_MASK	0x0F000000U /**< DMA
+								     Timeout
+								     Counter
+								     Value */
+#define XNANDPSU_SLV_DMA_CONF_SDMA_EN_MASK		0x10000000U /**< Slave
+								     DMA
+								     Enable */
+/* @} */
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+*
+* This macro reads the given register.
+*
+* @param	BaseAddress is the base address of controller registers.
+* @param	RegOffset is the register offset to be read.
+*
+* @return	The 32-bit value of the register.
+*
+* @note		C-style signature:
+*		u32 XNandPsu_ReadReg(u32 BaseAddress, u32 RegOffset)
+*
+*****************************************************************************/
+#define XNandPsu_ReadReg(BaseAddress, RegOffset)			\
+			Xil_In32((BaseAddress) + (RegOffset))
+
+/****************************************************************************/
+/**
+*
+* This macro writes the given register.
+*
+* @param	BaseAddress is the the base address of controller registers.
+* @param	RegOffset is the register offset to be written.
+* @param	Data is the the 32-bit value to write to the register.
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XNandPsu_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)
+*
+******************************************************************************/
+#define XNandPsu_WriteReg(BaseAddress, RegOffset, Data)			\
+			Xil_Out32(((BaseAddress) + (RegOffset)), (Data))
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* XNANDPSU_HW_H end of protection macro */
+/** @} */
diff --git a/bsps/include/dev/nand/xnandpsu_onfi.h b/bsps/include/dev/nand/xnandpsu_onfi.h
new file mode 100644
index 0000000000..7523ff48ea
--- /dev/null
+++ b/bsps/include/dev/nand/xnandpsu_onfi.h
@@ -0,0 +1,316 @@
+/******************************************************************************
+* Copyright (C) 2015 - 2022 Xilinx, Inc.  All rights reserved.
+* SPDX-License-Identifier: MIT
+******************************************************************************/
+
+/*****************************************************************************/
+/**
+*
+* @file xnandpsu_onfi.h
+* @addtogroup nandpsu_v1_10
+* @{
+*
+* This file defines all the ONFI 3.1 specific commands and values.
+*
+* @note		None
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date	   Changes
+* ----- ----   ----------  -----------------------------------------------
+* 1.0   nm     05/06/2014  First release
+* 1.4	nsk    04/10/2018  Added ICCARM compiler support.
+* </pre>
+*
+******************************************************************************/
+#ifndef XNANDPSU_ONFI_H		/* prevent circular inclusions */
+#define XNANDPSU_ONFI_H		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+#include "xil_types.h"
+
+/************************** Constant Definitions *****************************/
+/* Standard ONFI 3.1 Commands */
+/* ONFI 3.1 Mandatory Commands */
+#define ONFI_CMD_RD1			0x00U	/**< Read (1st cycle) */
+#define ONFI_CMD_RD2			0x30U	/**< Read (2nd cycle) */
+#define ONFI_CMD_CHNG_RD_COL1		0x05U	/**< Change Read Column
+						  (1st cycle) */
+#define ONFI_CMD_CHNG_RD_COL2		0xE0U	/**< Change Read Column
+						  (2nd cycle) */
+#define ONFI_CMD_BLK_ERASE1		0x60U	/**< Block Erase (1st cycle) */
+#define ONFI_CMD_BLK_ERASE2		0xD0U	/**< Block Erase (2nd cycle) */
+#define ONFI_CMD_RD_STS			0x70U	/**< Read Status */
+#define ONFI_CMD_PG_PROG1		0x80U	/**< Page Program(1st cycle) */
+#define ONFI_CMD_PG_PROG2		0x10U	/**< Page Program(2nd cycle) */
+#define ONFI_CMD_CHNG_WR_COL		0x85U	/**< Change Write Column */
+#define ONFI_CMD_RD_ID			0x90U	/**< Read ID */
+#define ONFI_CMD_RD_PRM_PG		0xECU	/**< Read Parameter Page */
+#define ONFI_CMD_RST			0xFFU	/**< Reset */
+/* ONFI 3.1 Optional Commands */
+#define ONFI_CMD_MUL_RD1		0x00U	/**< Multiplane Read
+						  (1st cycle) */
+#define ONFI_CMD_MUL_RD2		0x32U	/**< Multiplane Read
+						  (2nd cycle) */
+#define ONFI_CMD_CPBK_RD1		0x00U	/**< Copyback Read
+						  (1st cycle) */
+#define ONFI_CMD_CPBK_RD2		0x35U	/**< Copyback Read
+						  (2nd cycle) */
+#define ONFI_CMD_CHNG_RD_COL_ENHCD1	0x06U	/**< Change Read Column
+						  Enhanced (1st cycle) */
+#define ONFI_CMD_CHNG_RD_COL_ENHCD2	0xE0U	/**< Change Read Column
+						  Enhanced (2nd cycle) */
+#define ONFI_CMD_RD_CACHE_RND1		0x00U	/**< Read Cache Random
+						  (1st cycle) */
+#define ONFI_CMD_RD_CACHE_RND2		0x31U	/**< Read Cache Random
+						  (2nd cycle) */
+#define ONFI_CMD_RD_CACHE_SEQ		0x31U	/**< Read Cache Sequential */
+#define ONFI_CMD_RD_CACHE_END		0x3FU	/**< Read Cache End */
+#define ONFI_CMD_MUL_BLK_ERASE1		0x60U	/**< Multiplane Block Erase
+						  (1st cycle) */
+#define ONFI_CMD_MUL_BLK_ERASE2		0xD1U	/**< Multiplane Block Erase
+						  (2nd cycle) */
+#define ONFI_CMD_RD_STS_ENHCD		0x78U	/**< Read Status Enhanced */
+#define ONFI_CMD_BLK_ERASE_INTRLVD2	0xD1U	/**< Block Erase Interleaved
+						  (2nd cycle) */
+#define ONFI_CMD_MUL_PG_PROG1		0x80U	/**< Multiplane Page Program
+						  (1st cycle) */
+#define ONFI_CMD_MUL_PG_PROG2		0x11U	/**< Multiplane Page Program
+						  (2nd cycle) */
+#define ONFI_CMD_PG_CACHE_PROG1		0x80U	/**< Page Cache Program
+						  (1st cycle) */
+#define ONFI_CMD_PG_CACHE_PROG2		0x15U	/**< Page Cache Program
+						  (2nd cycle) */
+#define ONFI_CMD_CPBK_PROG1		0x85U	/**< Copyback Program
+						  (1st cycle) */
+#define ONFI_CMD_CPBK_PROG2		0x10U	/**< Copyback Program
+						  (2nd cycle) */
+#define ONFI_CMD_MUL_CPBK_PROG1		0x85U	/**< Multiplane Copyback
+						  Program (1st cycle) */
+#define ONFI_CMD_MUL_CPBK_PROG2		0x10U	/**< Multiplane Copyback
+						  Program (2nd cycle) */
+#define ONFI_CMD_SMALL_DATA_MV1		0x85U	/**< Small Data Move
+						  (1st cycle) */
+#define ONFI_CMD_SMALL_DATA_MV2		0x10U	/**< Small Data Move
+						  (2nd cycle) */
+#define ONFI_CMD_CHNG_ROW_ADDR		0x85U	/**< Change Row Address */
+#define ONFI_CMD_VOL_SEL		0xE1U	/**< Volume Select */
+#define ONFI_CMD_ODT_CONF		0xE2U	/**< ODT Configure */
+#define ONFI_CMD_RD_UNIQID		0xEDU	/**< Read Unique ID */
+#define ONFI_CMD_GET_FEATURES		0xEEU	/**< Get Features */
+#define ONFI_CMD_SET_FEATURES		0xEFU	/**< Set Features */
+#define ONFI_CMD_LUN_GET_FEATURES	0xD4U	/**< LUN Get Features */
+#define ONFI_CMD_LUN_SET_FEATURES	0xD5U	/**< LUN Set Features */
+#define ONFI_CMD_RST_LUN		0xFAU	/**< Reset LUN */
+#define ONFI_CMD_SYN_RST		0xFCU	/**< Synchronous Reset */
+
+/* ONFI Status Register bit offsets */
+#define ONFI_STS_FAIL			0x01U	/**< FAIL */
+#define ONFI_STS_FAILC			0x02U	/**< FAILC */
+#define ONFI_STS_CSP			0x08U	/**< CSP */
+#define ONFI_STS_VSP			0x10U	/**< VSP */
+#define ONFI_STS_ARDY			0x20U	/**< ARDY */
+#define ONFI_STS_RDY			0x40U	/**< RDY */
+#define ONFI_STS_WP			0x80U	/**< WP_n */
+
+/* ONFI constants */
+#define ONFI_CRC_LEN			254U	/**< ONFI CRC Buf Length */
+#define ONFI_PRM_PG_LEN			256U	/**< Parameter Page Length */
+#define ONFI_MND_PRM_PGS		3U	/**< Number of mandatory
+						  parameter pages */
+#define ONFI_SIG_LEN			4U	/**< Signature Length */
+#define ONFI_CMD_INVALID		0x00U	/**< Invalid Command */
+
+#define ONFI_READ_ID_LEN		4U	/**< ONFI ID length */
+#define ONFI_READ_ID_ADDR		0x20U	/**< ONFI Read ID Address */
+#define ONFI_READ_ID_ADDR_CYCLES	1U	/**< ONFI Read ID Address
+						  cycles */
+
+#define ONFI_PRM_PG_ADDR_CYCLES		1U	/**< ONFI Read Parameter page
+						  address cycles */
+
+/**
+ * This enum defines the ONFI 3.1 commands.
+ */
+enum OnfiCommandList {
+	READ=0,				/**< Read */
+	MULTIPLANE_READ,		/**< Multiplane Read */
+	COPYBACK_READ,			/**< Copyback Read */
+	CHANGE_READ_COLUMN,		/**< Change Read Column */
+	CHANGE_READ_COLUMN_ENHANCED,	/**< Change Read Column Enhanced */
+	READ_CACHE_RANDOM,		/**< Read Cache Random */
+	READ_CACHE_SEQUENTIAL,		/**< Read Cache Sequential */
+	READ_CACHE_END,			/**< Read Cache End */
+	BLOCK_ERASE,			/**< Block Erase */
+	MULTIPLANE_BLOCK_ERASE,		/**< Multiplane Block Erase */
+	READ_STATUS,			/**< Read Status */
+	READ_STATUS_ENHANCED,		/**< Read Status Enhanced */
+	PAGE_PROGRAM,			/**< Page Program */
+	MULTIPLANE_PAGE_PROGRAM,	/**< Multiplane Page Program */
+	PAGE_CACHE_PROGRAM,		/**< Page Cache Program */
+	COPYBACK_PROGRAM,		/**< Copyback Program */
+	MULTIPLANE_COPYBACK_PROGRAM,	/**< Multiplance Copyback Program */
+	SMALL_DATA_MOVE,		/**< Small Data Move */
+	CHANGE_WRITE_COLUMN,		/**< Change Write Column */
+	CHANGE_ROW_ADDR,		/**< Change Row Address */
+	READ_ID,			/**< Read ID */
+	VOLUME_SELECT,			/**< Volume Select */
+	ODT_CONFIGURE,			/**< ODT Configure */
+	READ_PARAM_PAGE,		/**< Read Parameter Page */
+	READ_UNIQUE_ID,			/**< Read Unique ID */
+	GET_FEATURES,			/**< Get Features */
+	SET_FEATURES,			/**< Set Features */
+	LUN_GET_FEATURES,		/**< LUN Get Features */
+	LUN_SET_FEATURES,		/**< LUN Set Features */
+	RESET_LUN,			/**< Reset LUN */
+	SYN_RESET,			/**< Synchronous Reset */
+	RESET,				/**< Reset */
+	MAX_CMDS			/**< Dummy Command */
+};
+
+/**************************** Type Definitions *******************************/
+/* Parameter page structure of ONFI 3.1 specification. */
+#ifdef __ICCARM__
+#pragma pack(push, 1)
+#endif
+typedef struct {
+	/* Revision information and features block */
+	u8 Signature[4];		/**< Parameter page signature */
+	u16 Revision;			/**< Revision Number */
+	u16 Features;			/**< Features supported */
+	u16 OptionalCmds;		/**< Optional commands supported */
+	u8 JedecJtgPrmAdvCmd;		/**< ONFI JEDEC JTG primary advanced
+					  command support */
+	u8 Reserved0;			/**< Reserved (11) */
+	u16 ExtParamPageLen;		/**< Extended Parameter Page Length */
+	u8 NumOfParamPages;		/**< Number of Parameter Pages */
+	u8 Reserved1[17];		/**< Reserved (15-31) */
+	/* Manufacturer information block */
+	u8 DeviceManufacturer[12];	/**< Device manufacturer */
+	u8 DeviceModel[20];		/**< Device model */
+	u8 JedecManufacturerId;		/**< JEDEC Manufacturer ID */
+	u8 DateCode[2];			/**< Date code */
+	u8 Reserved2[13];		/**< Reserved (67-79) */
+	/* Memory organization block */
+	u32 BytesPerPage;		/**< Number of data bytes per page */
+	u16 SpareBytesPerPage;		/**< Number of spare bytes per page */
+	u32 BytesPerPartialPage;	/**< Number of data bytes per
+					  partial page */
+	u16 SpareBytesPerPartialPage;	/**< Number of spare bytes per
+					  partial page */
+	u32 PagesPerBlock;		/**< Number of pages per block */
+	u32 BlocksPerLun;		/**< Number of blocks per LUN */
+	u8 NumLuns;			/**< Number of LUN's */
+	u8 AddrCycles;			/**< Number of address cycles */
+	u8 BitsPerCell;			/**< Number of bits per cell */
+	u16 MaxBadBlocksPerLun;		/**< Bad blocks maximum per LUN */
+	u16 BlockEndurance;		/**< Block endurance */
+	u8 GuaranteedValidBlock;	/**< Guaranteed valid blocks at
+					  beginning of target */
+	u16 BlockEnduranceGVB;		/**< Block endurance for guaranteed
+					  valid block */
+	u8 ProgramsPerPage;		/**< Number of programs per page */
+	u8 PartialProgAttr;		/**< Partial programming attributes */
+	u8 EccBits;			/**< Number of bits ECC
+					  correctability */
+	u8 PlaneAddrBits;		/**< Number of plane address bits */
+	u8 PlaneOperationAttr;		/**< Multi-plane operation
+					  attributes */
+	u8 EzNandSupport;		/**< EZ NAND support */
+	u8 Reserved3[12];		/**< Reserved (116 - 127) */
+	/* Electrical parameters block */
+	u8 IOPinCapacitance;		/**< I/O pin capacitance, maximum */
+	u16 SDRTimingMode;		/**< SDR Timing mode support */
+	u16 SDRPagecacheTimingMode;	/**< SDR Program cache timing mode */
+	u16 TProg;			/**< Maximum page program time */
+	u16 TBers;			/**< Maximum block erase time */
+	u16 TR;				/**< Maximum page read time */
+	u16 TCcs;			/**< Maximum change column setup
+					  time */
+	u8 NVDDRTimingMode;		/**< NVDDR timing mode support */
+	u8 NVDDR2TimingMode;		/**< NVDDR2 timing mode support */
+	u8 SynFeatures;			/**< NVDDR/NVDDR2 features */
+	u16 ClkInputPinCap;		/**< CLK input pin capacitance */
+	u16 IOPinCap;			/**< I/O pin capacitance */
+	u16 InputPinCap;		/**< Input pin capacitance typical */
+	u8 InputPinCapMax;		/**< Input pin capacitance maximum */
+	u8 DrvStrength;			/**< Driver strength support */
+	u16 TMr;			/**< Maximum multi-plane read time */
+	u16 TAdl;			/**< Program page register clear
+					  enhancement value */
+	u16 TEr;			/**< Typical page read time for
+					  EZ NAND */
+	u8 NVDDR2Features;		/**< NVDDR2 Features */
+	u8 NVDDR2WarmupCycles;		/**< NVDDR2 Warmup Cycles */
+	u8 Reserved4[4];		/**< Reserved (160 - 163) */
+	/* Vendor block */
+	u16 VendorRevisionNum;		/**< Vendor specific revision number */
+	u8 VendorSpecific[88];		/**< Vendor specific */
+	u16 Crc;			/**< Integrity CRC */
+#ifdef __ICCARM__
+} OnfiParamPage;
+#pragma pack(pop)
+#else
+}__attribute__((packed))OnfiParamPage;
+#endif
+
+/* ONFI extended parameter page structure. */
+#ifdef __ICCARM__
+#pragma pack(push, 1)
+#endif
+typedef struct {
+	u16 Crc;
+	u8 Sig[4];
+	u8 Reserved1[10];
+	u8 Section0Type;
+	u8 Section0Len;
+	u8 Section1Type;
+	u8 Section1Len;
+	u8 ResSection[12];
+	u8 SectionData[256];
+#ifdef __ICCARM__
+} OnfiExtPrmPage;
+#pragma pack(pop)
+#else
+}__attribute__((packed))OnfiExtPrmPage;
+#endif
+
+/* Driver extended parameter page information. */
+#ifdef __ICCARM__
+#pragma pack(push, 1)
+#endif
+typedef struct {
+	u8 NumEccBits;
+	u8 CodeWordSize;
+	u16 MaxBadBlocks;
+	u16 BlockEndurance;
+	u16 Reserved;
+#ifdef __ICCARM__
+} OnfiExtEccBlock;
+#pragma pack(pop)
+#else
+}__attribute__((packed))OnfiExtEccBlock;
+#endif
+
+typedef struct {
+	u8 Command1;			/**< Command Cycle 1 */
+	u8 Command2;			/**< Command Cycle 2 */
+} OnfiCmdFormat;
+
+extern const OnfiCmdFormat OnfiCmd[MAX_CMDS];
+
+/************************** Function Prototypes ******************************/
+
+u32 XNandPsu_OnfiParamPageCrc(u8 *ParamBuf, u32 StartOff, u32 Length);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* XNANDPSU_ONFI_H end of protection macro */
+/** @} */