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authorSebastian Huber <sebastian.huber@embedded-brains.de>2023-05-23 16:08:05 +0200
committerSebastian Huber <sebastian.huber@embedded-brains.de>2023-05-26 06:56:11 +0200
commitf69326d0c2b2ccc01507c8804c0caf06798be94f (patch)
tree73bfba33d0d8752f973c5e2c1d0cc90063e504f0 /bsps/arm/shared
parentarm: Improve Doxygen file comments (diff)
downloadrtems-f69326d0c2b2ccc01507c8804c0caf06798be94f.tar.bz2
bsps: Improve Doxygen file comments
Diffstat (limited to 'bsps/arm/shared')
-rw-r--r--bsps/arm/shared/cache/cache-cp15.h7
-rw-r--r--bsps/arm/shared/cache/cache-l2c-310.c15
-rw-r--r--bsps/arm/shared/cp15/arm-cp15-set-exception-handler.c9
-rw-r--r--bsps/arm/shared/cp15/arm-cp15-set-ttb-entries.c9
4 files changed, 31 insertions, 9 deletions
diff --git a/bsps/arm/shared/cache/cache-cp15.h b/bsps/arm/shared/cache/cache-cp15.h
index d717a8cf3f..7f1eb87812 100644
--- a/bsps/arm/shared/cache/cache-cp15.h
+++ b/bsps/arm/shared/cache/cache-cp15.h
@@ -1,11 +1,12 @@
/* SPDX-License-Identifier: BSD-2-Clause */
/**
+ * @file
+ *
* @ingroup RTEMSBSPsARMShared
*
- * @brief Level 1 Cache definitions and functions.
- *
- * This file implements handling for the ARM Level 1 cache controller
+ * @brief This header file provides interfaces of the ARM CP15 cache controller
+ * suppport.
*/
/*
diff --git a/bsps/arm/shared/cache/cache-l2c-310.c b/bsps/arm/shared/cache/cache-l2c-310.c
index 7bfa1a564c..6826043afd 100644
--- a/bsps/arm/shared/cache/cache-l2c-310.c
+++ b/bsps/arm/shared/cache/cache-l2c-310.c
@@ -1,9 +1,10 @@
/**
- * @ingroup L2C-310_cache
+ * @file
*
- * @brief Cache definitions and functions.
+ * @ingroup L2C310CacheSupport
*
- * This file implements handling for the ARM L2C-310 cache controller
+ * @brief This source file contains the implementation of the ARM L2C-310 cache
+ * controller support.
*/
/*
@@ -96,13 +97,15 @@
#define BSP_ARM_L2C_310_RTL_RELEASE (BSP_ARM_L2C_310_ID & L2C_310_ID_RTL_MASK)
/**
- * @defgroup L2C-310_cache Cache Support
+ * @defgroup L2C310CacheSupport L2C-310 Cache Support
+ *
* @ingroup RTEMSBSPsARMShared
- * @brief Cache Functions and Defitions
+ *
+ * @brief This group contains the L2C-310 cache support.
+ *
* @{
*/
-
/**
* @brief L2CC Register Offsets
*/
diff --git a/bsps/arm/shared/cp15/arm-cp15-set-exception-handler.c b/bsps/arm/shared/cp15/arm-cp15-set-exception-handler.c
index e97cd2dcbc..39f60e945e 100644
--- a/bsps/arm/shared/cp15/arm-cp15-set-exception-handler.c
+++ b/bsps/arm/shared/cp15/arm-cp15-set-exception-handler.c
@@ -1,5 +1,14 @@
/* SPDX-License-Identifier: BSD-2-Clause */
+/**
+ * @file
+ *
+ * @ingroup RTEMSBSPsARMShared
+ *
+ * @brief This source file contains the implementation of
+ * arm_cp15_set_exception_handler().
+ */
+
/*
* Copyright (c) 2013 embedded brains GmbH & Co. KG
*
diff --git a/bsps/arm/shared/cp15/arm-cp15-set-ttb-entries.c b/bsps/arm/shared/cp15/arm-cp15-set-ttb-entries.c
index bc8f2a26dd..25ee8103e4 100644
--- a/bsps/arm/shared/cp15/arm-cp15-set-ttb-entries.c
+++ b/bsps/arm/shared/cp15/arm-cp15-set-ttb-entries.c
@@ -1,5 +1,14 @@
/* SPDX-License-Identifier: BSD-2-Clause */
+/**
+ * @file
+ *
+ * @ingroup RTEMSBSPsARMShared
+ *
+ * @brief This source file contains the implementation of
+ * arm_cp15_set_translation_table_entries().
+ */
+
/*
* Copyright (C) 2010, 2019 embedded brains GmbH & Co. KG
*