| Commit message (Collapse) | Author | Age | Files | Lines |
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REGION_WORK may be backed by external RAM which may not be initialized
in a time we need stack to work well. E.g. code loaded in flash,
stack allocated on in-cpu SRAM and data (REGION_WORK) on external SDRAM.
Sponsored-By: Precidata
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Synchronize data and instruction streams.
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Updates #4625.
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Close #3250.
Close #4081.
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Do not continue execution on processors which are not configured to prevent the
use of arbitrary memory for the initialization stack.
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Do not return a status code in bsp_interrupt_facility_initialize() since this
leads to unreachable code in bsp_interrupt_initialize(). Use RTEMS_DEBUG
assertions in bsp_interrupt_facility_initialize() if necessary.
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Return a status code for bsp_interrupt_vector_disable().
Update #3269.
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Return a status code for bsp_interrupt_vector_enable().
Update #3269.
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Add a default implementation which just returns RTEMS_UNSATISFIED.
Update #3269.
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Add a default implementation which clears the attributes to zero and
just returns RTEMS_SUCCESSFUL for valid parameters.
Update #3269.
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Add rtems_interrupt_raise_on() and rtems_interrupt_clear().
Add a default implementation which just returns RTEMS_UNSATISFIED for
valid parameters.
Update #3269.
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Add a default implementation which just returns RTEMS_UNSATISFIED for
valid parameters.
Update #3269.
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Skip the data cache initialization if we are a secondary processor.
The bug was introduced by e164df5e33608576443b4cd5923a9046358ee773 and
did not show up in tests using Qemu since the data cache behaviour is
not emulated.
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Use BSP_INTERRUPT_VECTOR_COUNT instead of BSP_INTERRUPT_VECTOR_MAX.
Update #3269.
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Remove BSP_INTERRUPT_VECTOR_MIN and unconditionally let interrupt vector
numbers start with zero.
The BSP_INTERRUPT_VECTOR_MIN == 0 invariant was tested by the previous commit
and building all BSPs.
Update #3269.
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Update #3866.
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Set the Main Stack Pointer (MSP) to the ISR stack area end just in case
we run using the Process Stack Pointer (PSP). This helps if
applications are started by a boot loader.
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Update #3850
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Sort alphabetically.
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GCC 11 uses DWARF 5 by default.
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This avoids a function call overhead in the interrupt dispatching.
Update #4202.
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Update #4202.
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Initialize the data and unified cache levels. Invalidate the
instruction cache levels.
Update #4202.
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This makes it possible to reuse this loop.
Update #4202.
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The start hook arguments are not used by a BSP. Removing them avoids
the need for a stack during the very early system initialization.
Update #4202.
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Make sure the branch predictors are invalidated before the first branch
is executed.
Update #4202.
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Set the VBAR to the vector table in the start section before
bsp_start_hook_0() is called to earlier handle exceptions in RTEMS.
Set the VBAR to the normal vector table in start.S for the main
processor. Secondary processors set it in bsp_start_hook_0().
Update #4202.
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Avoid one level of indirection.
Update #4202.
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When moving the headers from the imx BSP to the shared area, the wrong
directory has been selected. This patch fixes that problem.
Update #4180
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Remove the target filter for software-generated interrupts since this
feature is not supported by the affinity routing in GICv3.
Update #4202.
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Use the targets parameter to determine the targets of the SGI. Change
targets parameter type to 32-bit to ease the parameter passing. GICv3
supports up to 16 targets.
Update #4202.
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Update #4202.
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This moves the ARM GICv2 driver to bsps/shared to be usable by AArch64
code.
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This moves the zynq-uart driver from bsps/arm/shared to bsps/shared to
accomodate use by AArch64 BSPs.
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Update #4180
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Update #4180
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Update #4180
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Update #3910.
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This breaks out AArch32-specific code so that the shared GICv3 code can
be reused by other architectures.
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This breaks AArch32-specific portions of the ARM GPT driver into their
own file so that the generic code can be moved for reuse by other
architectures.
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This UART driver is now needed for BSPs other than ARM.
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In a multi-processor system we must broadcast the TLB maintenance operation to
the Inner Shareable domain to ensure that the other processors update their TLB
caches accordingly.
Close #4068.
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Closes #4055
Closes #4056
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_CPU_Counter_frequency() can be called by the rtems_counter
initialization before arm_gt_clock_initialize() initializes the value
used in _CPU_Counter_frequency().
Closes #3961.
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Statically initialize the ARMv7-M vector table to allow a placement in
ROM with read-only MPU settings.
Change licence to BSD-2-Clause in some files.
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At least on GICv1 the interrupts 0 up to including 31 are so called
Peripheral Private Interrupts (PPIs). We have to initialize the
priority of the PPIs on secondary processors.
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