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* bsps/aarch64/raspberrypi: Add system timer supportHEADmasterNing Yang8 days2-5/+18
| | | | | | | | | | The clock from the ARM timer is derived from the system clock. This clock can change dynamically e.g. if the system goes into reduced power or in low power mode. Thus the clock speed adapts to the overall system performance capabilities. For accurate timing it is recommended to use the system timers. if BSP_CLOCK_USE_SYSTEMTIMER = 1, use the System Timer, otherwise use the ARM Timer.
* dev/irq: Improve Doxgyen group assignmentsSebastian Huber2024-04-161-2/+11
| | | | | Make the GIC interrupt controller support a subgroup of the generic interrupt controller support.
* bsps/arm: Improve GICv2 supportSebastian Huber2024-04-161-4/+8
| | | | | | | | In addtion to 1023, the GICC_IAR register may return 1022 as a special value. Simply check for a valid interrupt vector for the dispatching. Check the GICC_IAR again after the dispatch to quickly process a next interrupt without having to go through the interrupt prologue and epiloge.
* dev/serial: Add Zynq UART kernel I/O supportSebastian Huber2024-04-041-37/+4
| | | | | | Replace the BSP_CONSOLE_MINOR BSP option for the Xilinx Zynq BSPs with the new BSP option ZYNQ_UART_KERNEL_IO_BASE_ADDR. Move the kernel I/O support to a shared file.
* dev/serial: Add ZYNQ_UART_[01]_BASE_ADDRSebastian Huber2024-04-042-2/+4
| | | | This helps to provide a shared implementation of the kernel I/O support.
* dev/serial: Simplify some Zynq UART functionsSebastian Huber2024-03-271-17/+6
| | | | | | Make the initialization and polled functions independent of the Termios context. This helps to implement the kernel I/O support without a dependency on the Termios framework.
* bsps: Move declarations to <bsp/irq-generic.h>Sebastian Huber2024-03-271-28/+0
| | | | | | | | | | | Move declarations of bsp_interrupt_get_affinity() and bsp_interrupt_set_affinity() to <bsp/irq-generic.h>. Canonicalize the <bsp/irq.h> includes. Implement bsp_interrupt_get_affinity() and bsp_interrupt_set_affinity() only if needed (usually RTEMS_SMP). Provide stub implementations for i386 to fix build errors.
* aarch64/zynqmp: Fix UART base addresses and IRQSebastian Huber2024-03-112-4/+4
| | | | | The base addresses and IRQ numbers for UART 0 and 1 were interchanged. Fix this and set BSP_CONSOLE_MINOR to 0 for this BSP family.
* bsps/aarch64/cache: Clean up unused fuctionsKinsey Moore2024-01-101-27/+2
| | | | | | | | | When the CPU_CACHE_SUPPORT_PROVIDES_RANGE_FUNCTIONS definition was added to AArch64 cache management, it obsoleted the *_1_data/instruction_line functions. These have been removed since they are no longer referenced. The AArch64_instruction_cache_inner_shareable_invalidate_all function is only used when RTEMS_SMP is defined, so only define it in that circumstance.
* bsps/zynqmp/jffs2: Use BBT information directlyKinsey Moore2023-12-141-1/+23
| | | | | | | | The XNandPsu_IsBlockBad() function is insufficient for JFFS2 to determine whether a block is usable since the function does not report reserved blocks. JFFS2 is also unable to use the last 4 blocks of each target attached to the NAND controller since they are reserved for the Bad Block Table (BBT), but not necessarily marked as such.
* bsps/aarch64/zynqmp/nand: Erase using offsetKinsey Moore2023-10-271-8/+2
| | | | | | Prefer use of XNandPsu_Erase instead of XNandPsu_EraseBlock since the XNandPsu driver does not expose the primitives necessary to ensure device readiness after the operation is complete.
* bsps/aarch64: Disable use of TTBR1Tian Ye2023-10-181-1/+2
| | | | | | | Force use of addresses that would be translated by TTBR1 to cause a translation fault. RTEMS on AArch64 does not use TTBR1 and so attempted translation of that address range could cause unexpected behavior in the form of other exception types since TTBR1 is never set.
* bsps: Remove unused includesKinsey Moore2023-10-131-1/+0
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* bsps/xilinx-zynqmp: Unify JFFS2 OOB write lockingKinsey Moore2023-10-121-6/+17
| | | | | | | Ensure that a single locking session is carried over OOB writes including the OOB read that is sometimes required. This removes the possibility of another write occurring between the read and write that would make the write incorrect.
* bsps/zynqmp: Add locking around JFFS2 NAND adapterKinsey Moore2023-09-061-4/+26
| | | | | | The internal JFFS2 locking does not guarantee that delayed writes will not step on other reads and writes to the device. This adds locking to prevent that in the JFFS2 NAND interworking layer.
* aarch64/zynqmp: Use IRQs for management consoleKinsey Moore2023-07-032-1/+3
| | | | | Swap the zynqmp management console to interrupt-driven operation to avoid losing data in under-polled situations.
* xilinx-zynqmp: Include <rtems/termiostypes.h>Sebastian Huber2023-06-121-1/+1
| | | | Include <rtems/termiostypes.h> for the Termios device driver support.
* bsps/xqspipsu: Use device information from the FCTKinsey Moore2023-06-081-6/+6
| | | | | | Instead of statically defining the device parameters, use the device information available via the NOR device layer's Flash Configuration Table.
* xilinx-zynqmp: Include <rtems/libio.h> for rtems_termios_initialize()Joel Sherrill2023-06-061-0/+1
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* Update company nameSebastian Huber2023-05-202-2/+2
| | | | | The embedded brains GmbH & Co. KG is the legal successor of embedded brains GmbH.
* aarch64/versal: Fix uart interrupt issuesAaron Nyholm2023-05-161-1/+3
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* bsps/aarch64: Enable MMU during remapsKinsey Moore2023-04-181-3/+4
| | | | | | | | The MMU must be enabled during mapping changes and TLB invalidations. When this is not the case, TLB updates do not occur correctly in all cases. This is especially apparent when changing a block entry to a table entry when remapping small memory ranges in an otherwise contiguous block.
* bsps/zynqmp: Use correct include pathKinsey Moore2023-03-221-1/+1
| | | | | | The existing include path only works from inside the RTEMS build. This fixes the include path to work both in the RTEMS build and with builds of external apps since this file gets installed with the BSP.
* bsps/zynqmp: Add JFFS2 NAND adapterKinsey Moore2023-03-152-0/+382
| | | | | This adds the glue code necessary to allow JFFS2 to operate on top of NAND memory hosted by the XNandPsu peripheral/driver.
* bsps/aarch64: Disable interrupts during MMU remapKinsey Moore2023-02-271-0/+6
| | | | | | Interrupts must be disabled during MMU remapping since the majority of RTEMS including interrupts expects normal memory mapping semantics such as unaligned accesses.
* bsps/aarch64: Fix off-by-one cache bugKinsey Moore2023-02-141-16/+16
| | | | | | | The whole cache invalidation and flushing functions only ended up flusing the first N-1 levels of cache due to an off by one error. This resovles that issue and makes consistent the usage of levels as they relate to caching.
* bsps/aarch64: Flush cache before disabling MMUKinsey Moore2023-02-141-1/+7
| | | | | | To ensure data consistency, the cache much be flushed before disabling the MMU. When the MMU is disabled, all accesses are treated as non-cachced and thus will bypass the cache.
* bsps/xilinx-zynqmp: Add JFFS2 GQSPI NOR driverAlex White2023-01-273-0/+249
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* bsps: Move ZynqMP-specific info into the BSPKinsey Moore2023-01-041-0/+2
| | | | | | The address of the nandpsu peripheral is specific to the ZynqMP SoC and not relevant to other devices that might have one or more instances of this peripheral.
* bsps/zynqmp: Fix and update device treesKinsey Moore2022-12-074-115/+137
| | | | | | | | Add ref-clock-num identifiers to the device tree to ensure that interfaces use the correct clocks even when some are not used due to unconnected MII busses. This also adjusts the default ZynqMP PHY attachment to RGMII-ID which was the default before device trees were introduced.
* aarch64/versal: Add UART interrupt supportChris Johns2022-11-224-39/+324
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* rtems/versal: Updated mmu to include mapping for SDHCI devices on versalAaron Nyholm2022-11-221-1/+5
| | | | | | Tested on VCK190 Updates #4762
* bsps/zynqmp: Use direct fdt_* callsKinsey Moore2022-11-181-22/+10
| | | | | | This changes the ZynqMP device tree parsing over to direct libfdt calls to avoid inclusion of malloc() in the base BSP which currently causes sp01 to fail due to unexpected use of TLS space.
* aarch64/mmu: Prevent block descriptors at level -1Kinsey Moore2022-11-171-10/+13
| | | | | | | | | In the original implementation, level -1 was unused and all levels could have block-like descriptors (level 2 block descriptors are called page descriptors). When support for level -1 page tables was added the constraint on level -1 block descriptors was not honored. This prevents block descriptors from being mapped at level -1 since the hardware will not map them properly.
* bsps/aarch64: Ensure FPU trap state is consistentKinsey Moore2022-11-091-0/+6
| | | | | RTEMS may be booted from a dirty environment. Ensure that FPU trap settings are consistent.
* zynqmp: Add support for the CFC-400XKinsey Moore2022-11-098-1/+657
| | | | | | | | This adds a BSP variant for the ZynqMP BSP family to support the Innoflight CFC-400X platform. To properly support the CFC-400X, device trees were added to the ZynqMP platform due to both the optional management interface as well as alternate physical configuration of the ethernet interfaces.
* bsp/aarch64: Add new Raspberry Pi 4B BSPMohd Noor Aman2022-10-048-0/+957
| | | | | | | | | | | | | | | | | This patch adds new Raspberry pi 4B AArch64 BSP to the RTEMS Family. Currently only LP64 ABI is supported. ILP32 is not supported. RAM starts from 0x80000 in 64Bit kernel mode and MMU from 0x0. All Raspberrypi Pi 4B models and Raspberry Pi 400 are supported. All the IRQs are similiar to the older Raspberry pi 2 ARM BSP. Raspberry Pi 4B has 2 types of UARTs. Only PL011 serial is supported currently. Mini-UART is not supported. Mini-UART is default UART on the board so it needs to be disabled by adding "dtoverlay=disable-bt" to the config.txt. No support for additional 4 PL011-UARTs on the board. The raspberrypi.h includes many of the address required for the future development of the RPi 4B BSP. This includes peripherals, ARM Timer, VideoCore Timer, Watchdog, Mailbox, AUX, FIQs and IRQs.
* bsps/xilinx/versal: Add Cadence I2C driver supportChris Johns2022-08-254-0/+82
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* bsps: Fix .data.rel.ro placementSebastian Huber2022-08-121-1/+1
| | | | | | | The .data.rel.ro* linker input section pattern accidentally matches with writeable data those symbol name starts with "ro". Close #4701.
* aarch64/versal: Support DDRMC0 region 0 and 1Chris Johns2022-07-282-0/+58
| | | | | | | | | | | - Support DDRMC0 region 0 up to 2G in size - Support DDRMC0 region 1 with DDR memory greater than 2G up to the DDRMC0 max amount - Extend the heap with region 1's memory Closes #4684
* basp/aarch64: Make the unexpected sections origin address 64bitChris Johns2022-07-281-1/+1
| | | | Update #4684
* aarch64: Use page table level 0Kinsey Moore2022-07-212-15/+57
| | | | | | | | | This alters the AArch64 page table generation and mapping code and MMU configuration to use page table level 0 in addition to levels 1, 2, and 3. This allows the mapping of up to 48 bits of memory space and is the maximum that can be mapped without relying on additional processor extensions. Mappings are restricted based on the number of physical address bits that the CPU supports.
* aarch64: Memory map the noinit sectionKinsey Moore2022-07-182-0/+8
| | | | | This section was added recently and must be mapped to be accessed without generating an exception.
* bsps: Sort .noinit* sectionsSebastian Huber2022-07-151-1/+1
| | | | | | | | Sort the .noinit* input sections by name first, then by alignment if two sections have the same name. This allows the placement of begin/end symbols to initialize some areas with a special value. Update #4678.
* bsps/aarch64: Use MMU pages appropriatelyKinsey Moore2022-07-061-2/+2
| | | | | | | | | There were two bugs with MMU page use that were partially hiding each other. The linker script page table section was 4x the size it needed to be and the page table allocation routine was allocating pages PTRSIZE times larger than it needed to. On ILP32, this resulted in incorrect but functional allocation. On LP64, this resulted in allocation failures earlier than expected.
* bsp/aarch64: Flush the cache before invalidating itChris Johns2022-06-161-1/+2
| | | | | - Any page tables need to be flushed if the cache is enabled. Disabling the cache may only be available in secure mode.
* bsp/aarch64: Fix array warningChris Johns2022-06-111-1/+1
| | | | Updates #4664
* aarch64: always boot into EL1NSGedare Bloom2022-01-122-20/+29
| | | | | | | | | | | Always start the executive in Exception Level 1, Non-Secure mode. If we boot in EL3 Secure with GICv3 then we have to initialize the distributor and redistributor to set up G1NS interrupts early in the boot sequence before stepping down from EL3S to EL1NS. Now there is no need to distinguish between secure and non-secure world execution after the primary core boots, so get rid of the AARCH64_IS_NONSECURE configuration option.
* bsps/aarch64: refactor register init and hooksGedare Bloom2022-01-122-45/+48
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* bsps/aarch64: Support .noinit linker sectionSebastian Huber2021-12-131-0/+7
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