diff options
| author | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2024-04-08 14:49:21 +0200 |
|---|---|---|
| committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2024-04-16 07:26:35 +0200 |
| commit | 899f92f7b891f51c5ff1d62bb5c3f42bf73f23a0 (patch) | |
| tree | 069ba5ea3030e025dd17afbb190536a4b5e0136a /bsps/aarch64 | |
| parent | smptests/smpipi01: Fix sporadic test failure (diff) | |
| download | rtems-899f92f7b891f51c5ff1d62bb5c3f42bf73f23a0.tar.bz2 | |
bsps/arm: Improve GICv2 support
In addtion to 1023, the GICC_IAR register may return 1022 as a special value.
Simply check for a valid interrupt vector for the dispatching.
Check the GICC_IAR again after the dispatch to quickly process a next interrupt
without having to go through the interrupt prologue and epiloge.
Diffstat (limited to 'bsps/aarch64')
| -rw-r--r-- | bsps/aarch64/include/dev/irq/arm-gic-arch.h | 12 |
1 files changed, 8 insertions, 4 deletions
diff --git a/bsps/aarch64/include/dev/irq/arm-gic-arch.h b/bsps/aarch64/include/dev/irq/arm-gic-arch.h index f1b6fdc03d..94b832c2c5 100644 --- a/bsps/aarch64/include/dev/irq/arm-gic-arch.h +++ b/bsps/aarch64/include/dev/irq/arm-gic-arch.h @@ -46,14 +46,18 @@ extern "C" { #endif -static inline void arm_interrupt_handler_dispatch(rtems_vector_number vector) +static inline uint32_t arm_interrupt_enable_interrupts(void) { - uint32_t interrupt_level = _CPU_ISR_Get_level(); + uint32_t status = _CPU_ISR_Get_level(); /* Enable interrupts for nesting */ _CPU_ISR_Set_level(0); - bsp_interrupt_handler_dispatch(vector); + return status; +} + +static inline void arm_interrupt_restore_interrupts(uint32_t status) +{ /* Restore interrupts to previous level */ - _CPU_ISR_Set_level(interrupt_level); + _CPU_ISR_Set_level(status); } static inline void arm_interrupt_facility_set_exception_handler(void) |