Commit message (Collapse) | Author | Age | Files | Lines | |
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* | Update config.guess and config.sub | Sebastian Huber | 2018-07-06 | 2 | -1161/+1188 |
| | | | | | | | | | Update via: wget -O config.guess 'https://git.savannah.gnu.org/gitweb/?p=config.git;a=blob_plain;f=config.guess;hb=HEAD' wget -O config.sub 'https://git.savannah.gnu.org/gitweb/?p=config.git;a=blob_plain;f=config.sub;hb=HEAD' Update #3433. | ||||
* | bsps/arm: Include missing header file | Sebastian Huber | 2018-07-05 | 1 | -0/+1 |
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* | bsps: Update headers.am | Sebastian Huber | 2018-07-05 | 2 | -0/+9 |
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* | riscv: Clear reservations | Sebastian Huber | 2018-07-05 | 5 | -6/+25 |
| | | | | | | | See also RISC-V User-Level ISA V2.3, comment in section 8.2 "Load-Reserved/Store-Conditional Instructions". Update #3433. | ||||
* | posix: Check for new <pthread.h> prototypes | Sebastian Huber | 2018-07-05 | 5 | -9/+40 |
| | | | | | Update #3342. Update #3343. | ||||
* | riscv: Fix fcsr initialization | Sebastian Huber | 2018-07-02 | 2 | -1/+19 |
| | | | | Update #3433. | ||||
* | score: Increase PER_CPU_CONTROL_SIZE_APPROX | Sebastian Huber | 2018-06-29 | 1 | -1/+1 |
| | | | | | | Increase the PER_CPU_CONTROL_SIZE_APPROX on 64-bit targets. Update #3433. | ||||
* | riscv: Fix SMP context switch support | Sebastian Huber | 2018-06-29 | 1 | -2/+2 |
| | | | | Update #3433. | ||||
* | riscv: Add SMP context switch support | Sebastian Huber | 2018-06-29 | 1 | -0/+47 |
| | | | | Update #3433. | ||||
* | riscv: Add floating-point support | Sebastian Huber | 2018-06-29 | 8 | -50/+538 |
| | | | | Update #3433. | ||||
* | riscv: Fix global construction | Sebastian Huber | 2018-06-29 | 3 | -6/+7 |
| | | | | Update #3433. | ||||
* | riscv: Add TLS support | Sebastian Huber | 2018-06-29 | 2 | -0/+9 |
| | | | | Update #3433. | ||||
* | riscv: Remove dead code | Sebastian Huber | 2018-06-29 | 1 | -41/+1 |
| | | | | Update #3433. | ||||
* | riscv: Optimize context switch and interrupts | Sebastian Huber | 2018-06-29 | 6 | -174/+255 |
| | | | | | | | | Save/restore non-volatile registers in _CPU_Context_switch(). Save/restore volatile registers in _ISR_Handler(). Update #3433. | ||||
* | riscv: Fix _CPU_Context_Initialize() prototype | Sebastian Huber | 2018-06-29 | 2 | -12/+12 |
| | | | | Update #3433. | ||||
* | riscv: Fix interrupt save/restore | Sebastian Huber | 2018-06-29 | 1 | -1/+1 |
| | | | | Update #3433. | ||||
* | riscv: Implement _CPU_Context_validate() | Sebastian Huber | 2018-06-29 | 2 | -160/+168 |
| | | | | Update #3433. | ||||
* | riscv: Make some CPU port defines visible to asm | Sebastian Huber | 2018-06-29 | 2 | -37/+49 |
| | | | | | | Move SREG and LREG assembler defines to <rtems/score/asm.h>. Update #3433. | ||||
* | riscv: Implement _CPU_Context_volatile_clobber() | Sebastian Huber | 2018-06-29 | 2 | -16/+16 |
| | | | | Update #3433. | ||||
* | riscv: Remove mstatus from thread context | Sebastian Huber | 2018-06-29 | 4 | -27/+14 |
| | | | | | | | | | | The mstatus register contains no thread-specific state which must be saved/restored during a context switch. Machine interrupts (MIE) must be enabled during a context switch. Create separate CPU_Interrupt_frame structure. Update #3433. | ||||
* | riscv: Remove x8 initialization | Sebastian Huber | 2018-06-29 | 1 | -2/+0 |
| | | | | | | | | | | The RISC-V psABI https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md does not mention that this is a frame pointer. Update #3433. | ||||
* | riscv: Properly align the thread stack | Sebastian Huber | 2018-06-29 | 1 | -3/+7 |
| | | | | Update #3433. | ||||
* | riscv: Do not clear thread context | Sebastian Huber | 2018-06-29 | 1 | -5/+2 |
| | | | | | | | | Do not clear the complete thread context. Initialize only the necessary members. The Context_Control::is_executing member must be preserved across _CPU_Context_Initialize() calls. Update #3433. | ||||
* | riscv: Fix CPU_STACK_ALIGNMENT | Sebastian Huber | 2018-06-29 | 1 | -1/+2 |
| | | | | | | | | | | According to the RISC-V psABI https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md the stack alignment is 128 bits (16 bytes). Update #3433. | ||||
* | riscv: Remove RISCV_GCC_RED_ZONE_SIZE | Sebastian Huber | 2018-06-29 | 2 | -5/+1 |
| | | | | | | | | | | | The current ABI says that there is no stack red zone: https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md "Procedures must not rely upon the persistence of stack-allocated data whose addresses lie below the stack pointer." Update #3433. | ||||
* | riscv: Enable interrupts during dispatch after ISR | Sebastian Huber | 2018-06-29 | 5 | -55/+91 |
| | | | | | | | | The code sequence is derived from the ARM code (see _ARMV4_Exception_interrupt). Update #2751. Update #3433. | ||||
* | riscv: Add _CPU_Get_current_per_CPU_control() | Sebastian Huber | 2018-06-28 | 3 | -1/+28 |
| | | | | Update #3433. | ||||
* | riscv: Avoid namespace pollution | Sebastian Huber | 2018-06-28 | 4 | -10/+5 |
| | | | | | | | Remove <rtems/score/riscv-utility.h> include from <rtems/score/cpu.h> (which is visible via <rtems.h> for example). Update #3433. | ||||
* | riscv: Optimize and fix interrupt disable/enable | Sebastian Huber | 2018-06-28 | 1 | -15/+16 |
| | | | | | | | | | Use the atomic read and clear operation to disable interrupts. Do not write the complete mstatus. Instead, set only the MIE bit depending on the level parameter. Update #3433. | ||||
* | bsp/riscv: Remove bsp_interrupt_handler_default() | Sebastian Huber | 2018-06-28 | 1 | -9/+0 |
| | | | | | | It duplicated the default implementation. Update #3433. | ||||
* | bsp/riscv: Rework clock driver | Sebastian Huber | 2018-06-28 | 4 | -65/+125 |
| | | | | | | | Use device tree provided timebase frequency. Do not write to read-only mtime register. Update #3433. | ||||
* | bsp/riscv: Add device tree support for console | Sebastian Huber | 2018-06-28 | 5 | -65/+222 |
| | | | | Update #3433. | ||||
* | bsp/riscv: Fix vector table for lp64 | Sebastian Huber | 2018-06-28 | 1 | -16/+22 |
| | | | | Update #3433. | ||||
* | bsp/riscv: Add SMP startup synchronization | Sebastian Huber | 2018-06-28 | 1 | -2/+20 |
| | | | | Update #3433. | ||||
* | bsp/riscv: Add device tree support | Sebastian Huber | 2018-06-28 | 4 | -6/+27 |
| | | | | Update #3433. | ||||
* | riscv: Add dummy SMP support | Sebastian Huber | 2018-06-28 | 5 | -126/+42 |
| | | | | Update #3433. | ||||
* | build: Enable RISC-V SMP build | Sebastian Huber | 2018-06-28 | 3 | -3/+3 |
| | | | | Update #3433. | ||||
* | riscv: Implement ISR set/get level | Sebastian Huber | 2018-06-28 | 2 | -9/+18 |
| | | | | | | Fix prototypes. Update #3433. | ||||
* | bsp/riscv: Load global pointer | Sebastian Huber | 2018-06-27 | 2 | -2/+6 |
| | | | | Update #3433. | ||||
* | bsp/riscv: Use memset() to clear .bss | Sebastian Huber | 2018-06-27 | 1 | -10/+5 |
| | | | | Update #3433. | ||||
* | riscv: Format assembler files | Sebastian Huber | 2018-06-27 | 5 | -468/+473 |
| | | | | | | Use tabs to match the GCC generated assembler output. Update #3433. | ||||
* | bsp/riscv: Do not clear integer registers at start | Sebastian Huber | 2018-06-27 | 1 | -31/+0 |
| | | | | | | There is no need to do this. Update #3433. | ||||
* | bsp/riscv: Fix some warnings | Sebastian Huber | 2018-06-27 | 1 | -20/+4 |
| | | | | Update #3444. | ||||
* | bsp/riscv: Add BSP options to define RAM region | Sebastian Huber | 2018-06-27 | 2 | -3/+25 |
| | | | | Update #3433. | ||||
* | bsp/riscv: Remove unused BSP options | Sebastian Huber | 2018-06-27 | 1 | -10/+0 |
| | | | | Update #3433. | ||||
* | bsp/riscv: Add new BSP variants | Sebastian Huber | 2018-06-27 | 5 | -0/+45 |
| | | | | | | | The latest RISC-V tool chain introduced new multilib variants. Add corresponding BSP variants. Update #3433. | ||||
* | bsp/riscv_generic: Rename to "riscv" | Sebastian Huber | 2018-06-27 | 24 | -22/+22 |
| | | | | Update #3433. | ||||
* | bsp/riscv_generic: Use standard optimization flags | Sebastian Huber | 2018-06-27 | 7 | -7/+21 |
| | | | | Update #3433. | ||||
* | bsps/riscv_generic: Rename and add variants | Hesham Almatary | 2018-06-27 | 7 | -2/+37 |
| | | | | Add BSP variants to match supported RISC-V ISA variants (multilibs). | ||||
* | bsp/riscv_generic: New linker command file | Sebastian Huber | 2018-06-27 | 5 | -341/+392 |
| | | | | | | | This linker command file is based on the "riscv64-rtems5-ld --verbose" output. Update #3433. |