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| author | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2018-06-28 13:04:58 +0200 |
|---|---|---|
| committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2018-06-28 15:02:13 +0200 |
| commit | c558cc4b00f00b6746eec3a249a7a79995cea7cf (patch) | |
| tree | f8d9c1cc44249686bce2e95d3b81200355184c16 | |
| parent | bsp/riscv: Add SMP startup synchronization (diff) | |
| download | rtems-c558cc4b00f00b6746eec3a249a7a79995cea7cf.tar.bz2 | |
bsp/riscv: Fix vector table for lp64
Update #3433.
| -rw-r--r-- | bsps/riscv/riscv/start/start.S | 38 |
1 files changed, 22 insertions, 16 deletions
diff --git a/bsps/riscv/riscv/start/start.S b/bsps/riscv/riscv/start/start.S index b59e55f2ea..390459a1fb 100644 --- a/bsps/riscv/riscv/start/start.S +++ b/bsps/riscv/riscv/start/start.S @@ -104,22 +104,28 @@ SYM(_start): .word 0xdeadbeef #endif +#if __riscv_xlen == 32 +#define ADDR .word +#elif __riscv_xlen == 64 +#define ADDR .quad +#endif + .align 4 bsp_start_vector_table_begin: - .word _RISCV_Exception_default /* User int */ - .word _RISCV_Exception_default /* Supervisor int */ - .word _RISCV_Exception_default /* Reserved */ - .word _RISCV_Exception_default /* Machine int */ - .word _RISCV_Exception_default /* User timer int */ - .word _RISCV_Exception_default /* Supervisor Timer int */ - .word _RISCV_Exception_default /* Reserved */ - .word _RISCV_Exception_default /* Machine Timer int */ - .word _RISCV_Exception_default /* User external int */ - .word _RISCV_Exception_default /* Supervisor external int */ - .word _RISCV_Exception_default /* Reserved */ - .word _RISCV_Exception_default /* Machine external int */ - .word _RISCV_Exception_default - .word _RISCV_Exception_default - .word _RISCV_Exception_default - .word _RISCV_Exception_default + ADDR _RISCV_Exception_default /* User int */ + ADDR _RISCV_Exception_default /* Supervisor int */ + ADDR _RISCV_Exception_default /* Reserved */ + ADDR _RISCV_Exception_default /* Machine int */ + ADDR _RISCV_Exception_default /* User timer int */ + ADDR _RISCV_Exception_default /* Supervisor Timer int */ + ADDR _RISCV_Exception_default /* Reserved */ + ADDR _RISCV_Exception_default /* Machine Timer int */ + ADDR _RISCV_Exception_default /* User external int */ + ADDR _RISCV_Exception_default /* Supervisor external int */ + ADDR _RISCV_Exception_default /* Reserved */ + ADDR _RISCV_Exception_default /* Machine external int */ + ADDR _RISCV_Exception_default + ADDR _RISCV_Exception_default + ADDR _RISCV_Exception_default + ADDR _RISCV_Exception_default bsp_start_vector_table_end: |