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| author | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2018-06-22 13:30:21 +0200 |
|---|---|---|
| committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2018-06-27 08:58:18 +0200 |
| commit | 9b2ef07f4b2307c2ea7c057918643747e8e2f4a4 (patch) | |
| tree | 3d06b312925015e2ceda50bbdea1da90a1ba833e | |
| parent | bsp/riscv: Use memset() to clear .bss (diff) | |
| download | rtems-9b2ef07f4b2307c2ea7c057918643747e8e2f4a4.tar.bz2 | |
bsp/riscv: Load global pointer
Update #3433.
| -rw-r--r-- | bsps/riscv/riscv/start/start.S | 6 | ||||
| -rw-r--r-- | cpukit/score/cpu/riscv/riscv-context-switch.S | 2 |
2 files changed, 6 insertions, 2 deletions
diff --git a/bsps/riscv/riscv/start/start.S b/bsps/riscv/riscv/start/start.S index 3674a4bdb5..58bc57dc12 100644 --- a/bsps/riscv/riscv/start/start.S +++ b/bsps/riscv/riscv/start/start.S @@ -46,6 +46,12 @@ PUBLIC(_start) TYPE_FUNC(_start) SYM(_start): + /* Load global pointer */ + .option push + .option norelax + la gp, __global_pointer$ + .option pop + la t0, ISR_Handler csrw mtvec, t0 diff --git a/cpukit/score/cpu/riscv/riscv-context-switch.S b/cpukit/score/cpu/riscv/riscv-context-switch.S index 448a5991a0..705cd77175 100644 --- a/cpukit/score/cpu/riscv/riscv-context-switch.S +++ b/cpukit/score/cpu/riscv/riscv-context-switch.S @@ -51,7 +51,6 @@ SYM(_CPU_Context_switch): SREG x1, (1 * CPU_SIZEOF_POINTER)(a0) SREG x2, (2 * CPU_SIZEOF_POINTER)(a0) - SREG x3, (3 * CPU_SIZEOF_POINTER)(a0) SREG x4, (4 * CPU_SIZEOF_POINTER)(a0) SREG x5, (5 * CPU_SIZEOF_POINTER)(a0) SREG x6, (6 * CPU_SIZEOF_POINTER)(a0) @@ -85,7 +84,6 @@ SYM(_CPU_Context_switch): LREG x1, (1 * CPU_SIZEOF_POINTER)(a1) LREG x2, (2 * CPU_SIZEOF_POINTER)(a1) - LREG x3, (3 * CPU_SIZEOF_POINTER)(a1) LREG x4, (4 * CPU_SIZEOF_POINTER)(a1) LREG x5, (5 * CPU_SIZEOF_POINTER)(a1) LREG x6, (6 * CPU_SIZEOF_POINTER)(a1) |