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author | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2018-06-22 09:03:19 +0200 |
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committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2018-06-27 08:58:17 +0200 |
commit | fef0a414cf9ee2ef0f3557687f3b9139e48af9f5 (patch) | |
tree | 2b97f64957cc33c915e19722a655c948771f1c34 | |
parent | bsp/riscv: Fix some warnings (diff) | |
download | rtems-fef0a414cf9ee2ef0f3557687f3b9139e48af9f5.tar.bz2 |
bsp/riscv: Do not clear integer registers at start
There is no need to do this.
Update #3433.
-rw-r--r-- | bsps/riscv/riscv/start/start.S | 31 |
1 files changed, 0 insertions, 31 deletions
diff --git a/bsps/riscv/riscv/start/start.S b/bsps/riscv/riscv/start/start.S index ac5b6a96ef..1ed46f07e4 100644 --- a/bsps/riscv/riscv/start/start.S +++ b/bsps/riscv/riscv/start/start.S @@ -43,37 +43,6 @@ PUBLIC(_start) .section .bsp_start_text, "wax" TYPE_FUNC(_start) SYM(_start): - li x2, 0 - li x3, 0 - li x4, 0 - li x5, 0 - li x6, 0 - li x7, 0 - li x8, 0 - li x9, 0 - li x10, 0 - li x11, 0 - li x12, 0 - li x13, 0 - li x14, 0 - li x15, 0 - li x16, 0 - li x17, 0 - li x18, 0 - li x19, 0 - li x20, 0 - li x21, 0 - li x22, 0 - li x23, 0 - li x24, 0 - li x25, 0 - li x26, 0 - li x27, 0 - li x28, 0 - li x29, 0 - li x30, 0 - li x31, 0 - la t0, ISR_Handler csrw mtvec, t0 |