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| author | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2018-06-27 08:57:08 +0200 |
|---|---|---|
| committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2018-06-29 10:04:37 +0200 |
| commit | 8f035cb85aff739de9bd33c4ad20d2e26bc3fee5 (patch) | |
| tree | b1f4197ad35a2d203b066bfd2db0fa896b225015 | |
| parent | riscv: Remove mstatus from thread context (diff) | |
| download | rtems-8f035cb85aff739de9bd33c4ad20d2e26bc3fee5.tar.bz2 | |
riscv: Implement _CPU_Context_volatile_clobber()
Update #3433.
| -rw-r--r-- | cpukit/score/cpu/riscv/include/rtems/score/cpu.h | 5 | ||||
| -rw-r--r-- | cpukit/score/cpu/riscv/riscv-context-volatile-clobber.S | 27 |
2 files changed, 16 insertions, 16 deletions
diff --git a/cpukit/score/cpu/riscv/include/rtems/score/cpu.h b/cpukit/score/cpu/riscv/include/rtems/score/cpu.h index 8821c0e4ec..1329b3e724 100644 --- a/cpukit/score/cpu/riscv/include/rtems/score/cpu.h +++ b/cpukit/score/cpu/riscv/include/rtems/score/cpu.h @@ -415,10 +415,7 @@ static inline uint32_t CPU_swap_u32( #define CPU_swap_u16( value ) \ (((value&0xff) << 8) | ((value >> 8)&0xff)) -static inline void _CPU_Context_volatile_clobber( uintptr_t pattern ) -{ - /* TODO */ -} +void _CPU_Context_volatile_clobber( uintptr_t pattern ); static inline void _CPU_Context_validate( uintptr_t pattern ) { diff --git a/cpukit/score/cpu/riscv/riscv-context-volatile-clobber.S b/cpukit/score/cpu/riscv/riscv-context-volatile-clobber.S index 7607e9d5bc..9d3d39b32d 100644 --- a/cpukit/score/cpu/riscv/riscv-context-volatile-clobber.S +++ b/cpukit/score/cpu/riscv/riscv-context-volatile-clobber.S @@ -1,4 +1,5 @@ /* + * Copyright (c) 2018 embedded brains GmbH * Copyright (c) 2015 Hesham Almatary <hesham@alumni.york.ac.uk> * * Redistribution and use in source and binary forms, with or without @@ -35,17 +36,19 @@ PUBLIC(_CPU_Context_volatile_clobber) SYM(_CPU_Context_volatile_clobber): - .macro clobber_register reg - addi t0, t0, -1 - mv \reg, t0 - .endm - - clobber_register a0 - clobber_register a1 - clobber_register a2 - clobber_register a3 - clobber_register a4 - clobber_register a5 - clobber_register a6 + addi a1, a0, 1 + addi a2, a0, 2 + addi a3, a0, 3 + addi a4, a0, 4 + addi a5, a0, 5 + addi a6, a0, 6 + addi a7, a0, 7 + addi t0, a0, 8 + addi t1, a0, 9 + addi t2, a0, 10 + addi t3, a0, 11 + addi t4, a0, 12 + addi t5, a0, 13 + addi t6, a0, 14 ret |