| Commit message (Collapse) | Author | Age | Files | Lines |
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Add default memory attributes for read-write data. The actual
attributes depend on the RTEMS_SMP build option.
Update #4202.
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Fix definition of AARCH32_PMSA_DATA_READ_WRITE_CACHED. Since
AARCH32_PMSA_ATTR_AP_EL1_RW_EL0_NO is zero, this fix is only cosmetic.
Update #4202.
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Affected components are the GR712RC, UT699, UT699E, UT700, and
LEON3FT-RTAX. Strictly, the workaround is only necessary if the MMU is
enabled. Use __FIX_LEON3FT_B2BST to enable the workaround. This is not
100% appropriate, but the best thing we can use to enable the
workaround.
Close #4551.
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These two OAR copyright headers are the only two in the codebase with
a format that differs from the typical OAR copyright header. This makes
all of the OAR copyright headers consistent.
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The existing code is functional but inccorrect and blindly modifies the
other masking bits. It is important to preserve those other bits since
they control masking of important system events.
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This moves the AArch64 MMU memory type definitions into cpukit for use
by libdebugger since remapping of memory is required to insert software
breakpoints.
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The N used in the breakpoint and watchpoint register names is intended
to be an integer between 0 and 15 (inclusive) and will not compile when
used as is. This adds the accessors necessary to access all of these
breakpoint and watchpoint registers.
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This adds the function implementations necessary to add exception
extensions support to AArch64.
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This adds the set of functions necessary to allow more generic handling
of machine exceptions. This initial patch offers the ability to
manipulate a CPU_Exception_frame and resume execution using that
exception information with or without thread dispatch. These functions
are gated behind the RTEMS_EXCEPTION_EXTENSIONS configuration option.
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This reworks the existing MicroBlaze architecture port and BSP to
achieve basic functionality using the latest RTEMS APIs.
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All other architectures use uint32_t for interrupt levels and there is
no reason not to do so on AArch64.
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Context validation for AArch64 was ported from the ARM implementation
without a reinterpretation of the actual requirements. The spcontext01
test just happened to pass because the set of scratch registers in ARM
is a subset of the scratch registers in AArch64.
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This adds SMP support for AArch64 in cpukit and for the ZynqMP BSPs.
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Close #3250.
Close #4081.
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Cloning under Cygwin turned off executable permission on these
files. This shows them as modified even though they have not
explicitly been touched. Executable permission should not have
been on for these files so this is just a minor clean up.
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Move _CPU_Fatal_halt() declaration to <rtems/score/cpuimpl.h> and make sure it
is a proper declaration of a function which does not return. Fix the type of
the error code. If necessary, add the implementation to cpu.c. Implementing
_CPU_Fatal_halt() as a function makes it possible to wrap this function for
example to fully test _Terminate().
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Remove _CPU_SMP_Processor_event_broadcast() and
_CPU_SMP_Processor_event_receive(). These functions are hard to use since they
are subject to the lost wake up problem.
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Prefer RTEMS_FATAL_SOURCE_EXCEPTION over
INTERNAL_ERROR_ILLEGAL_USE_OF_FLOATING_POINT_UNIT since the fatal code
(rtems_exception_frame) provides more context.
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The Cortex-R52 does not support cache coherency and the shareable memory
attribute. If a region is configured to be shareable, then it falls
back to use non-cacheable memory.
Update #4202.
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Update #4202.
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Update #4202.
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Disable the alignment check through SCTLR[A] in
_AArch32_PMSA_Initialize().
Update #4202.
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Move _ISR_Handler() to a separate file since it is now only used if a handler
is installed by _CPU_ISR_install_raw_handler().
Statically initialize the traps for external interrupts to use the new
_SPARC_Interrupt_trap() which directly dispatches the interrupt handlers
installed by rtems_interrupt_handler_install() via the BSP-provided
_SPARC_Interrupt_dispatch().
Since the trap table is now fully statically initialized, there is no longer a
dependency on the Cache Manager in the default configuration.
Update #4458.
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This makes them usable in multiple files.
Update #4458.
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Statically initialize the trap table in start.S to jump to _SPARC_Bad_trap()
for all unexpected traps. This enables a proper RTEMS fatal error handling
right from the start. Do not rely on the stack and register settings which
caused an unexpected trap. Use the ISR stack of the processor to do the fatal
error handling. Save the full context which caused the trap. Fatal error
handler may use it for error logging.
Unify the _CPU_Exception_frame_print() implementations and move it to cpukit.
Update #4459.
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Move _CPU_ISR_install_raw_handler() and _CPU_ISR_install_vector() to separate
files. The goal is to make their use optional.
Update #4458.
Update #4459.
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This CPU port macro was not used. Since the _ISR_Vector_table[] is statically
allocated, CPU ports could initialize this table in _CPU_Initialize() if
necessary. Remove _CPU_Initialize_vectors() to simplify the CPU port
interface.
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The write to RBAR didn't have the valid flag set. Therefore the write to
RASR had an influence on the previously set region. That means for
example that if Region 0 had been enabled but 1 should be disabled due
to a size of 0, the previous code would have disabled region 0 instead.
This patch fixes that behaviour.
Close #4450
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Don't initialze regions that have a negative size (for example due to a
wrong calculation).
Update #4450
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Update #4202.
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Currently, the AArch64 BSPs have a hard time running on real hardware
without building the toolchain and the bsps with -mstrict-align in
multiple places. Configuring the MMU on these chips allows for unaligned
memory accesses for non-device memory which avoids requiring strict
alignment in the toolchain and in the BSPs themselves.
In writing this driver, it was found that the synchronous exception
handling code needed to be rewritten since it relied on clearing SCTLR_EL1 to
avoid thread stack misalignments in RTEMS_DEBUG mode. This is now
avoided by exactly preserving thread mode stack and flags and the new
implementation is compatible with the draft information provided on the
mailing list covering the Exception Management API.
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Break out system register definitions and accessors so that they're
usable by other parts of RTEMS.
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Ensure the stack remains aligned by keeping the context frame at a
multiple of 16 bytes. This avoids stack alignment exceptions which occur
when the stack pointer is not 16 byte aligned.
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The __builtin_unreachable() cannot be used with current GCC versions to
tell the compiler that a function does not return to the caller, see:
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99151
Add a no return variant of _CPU_Context_switch() to avoid generation of
dead code in _Thread_Start_multitasking() if RTEMS was built with SMP
support enabled.
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The _CPU_ISR_Is_enabled() function operates on ISR cookies and so must
mask off the appropriate status bits. This also fixes the naming of the
parameters of the _CPU_ISR_* functions to indicate use of ISR cookies
instead of interrupt enable/disable levels.
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Overview
========
The errata is worked around in the kernel without requiring toolchain
modifications. It is triggered the JMPL/RETT return from trap instruction
sequence never generated by the compiler and. There are also other
conditions that must must be true to trigger the errata, for example the
instruction that the trap returns to has to be a JMPL instruction. The
errata can only be triggered if certain data is corrected by ECC
(inflicted by radiation), thus it can not be triggered under normal
operation. For more information see:
www.gaisler.com/notes
Affected RTEMS target BSPs:
* GR712RC
* UT699
* UT700/699E
The work around is enabled by defining __FIX_LEON3_TN0018 at build time.
After applying the following GCC patch, GCC will set the define when
compiling for an affected multilib:
* GR712RC (-mcpu=leon3 -mfix-gr712rc)
* UT700/UT699E (-mpcu=leon3 -mfix-ut700)
* UT699 (-mcpu=leon -mfix-ut699)
When building for another multilib and TN0018 is still required, it
is possible to enable it on the RTEMS kernel configure line using the
TARGET_CFLAGS (-D__FIX_LEON3FT_TN0018) or other by other means.
The following GCC patch sets __FIX_LEON3FT_TN0018 for the affected RTEMS
multilibs:
---------
diff --git a/gcc/config/sparc/rtemself.h b/gcc/config/sparc/rtemself.h
index 6570590..ddec98c 100644
--- a/gcc/config/sparc/rtemself.h
+++ b/gcc/config/sparc/rtemself.h
@@ -33,6 +33,8 @@
builtin_assert ("system=rtems"); \
if (sparc_fix_b2bst) \
builtin_define ("__FIX_LEON3FT_B2BST"); \
+ if (sparc_fix_gr712rc || sparc_fix_ut700 || sparc_fix_ut699) \
+ builtin_define ("__FIX_LEON3FT_TN0018"); \
} \
while (0)
---------
Workaround Implementation
=========================
In general there are two approaches that the workaround uses:
A) avoid ECC restarting the RETT instruction
B) avoid returning from trap to a JMPL instruction
Where A) comes at a higher performance cost than B), so B) is used
where posssible. B) can be achived for certain returns from trap
handlers if trap entry is controlled by assembly, such as system calls.
A)
A special JMPL/RETT sequence where instruction cache is disabled
temporarily to avoid RETT containing ECC errors, and reading of RETT
source registers to "clean" them from incorrect ECC just before RETT
is executed.
B)
The work around prevents JMPL after system calls (TA instruction) and
modifies assembly code on return from traps jumping back to application
code. Note that for some traps the trapped instruction is always
re-executed and can therefore not trigger the errata, for example the
SAVE instruction causing window overflow or an float instruction causing
FPU disabled trap.
RTEMS SPARC traps workaround implementation:
NAME NOTE TRAP COMMENT
* window overflow 1 - 0x05 always returns to a SAVE
* window underflow 1 - 0x06 always returns to a RESTORE
* interrupt traps 2 - 0x10..1f special rett sequence workaround
* syscall 3 - 0x80 shutdown system - never returns
* ABI flush windows 2 - 0x83 special rett sequence workaround
* syscall_irqdis 4 - 0x89
* syscall_irqen 4 - 0x8A
* syscall_irqdis_fp 1 - 0x8B always jumps back to FP instruction
* syscall_lazy_fp_switch 5 - 0x04 A) jumps back to FP instruction, or to
B) _Internal_error() starting with SAVE
Notes:
1) no workaround needed because trap always returns to non-JMPL instruction
2) workaround implemented by special rett sequence
3) no workaround needed because system call never returns
4) workaround implemented by inserting NOP in system call generation. Thus
fall into 1) when workaround is enabled and no trap handler fix needed.
5) trap handler branches into both 1) and returning to _Internal_error()
which starts with a SAVE and besides since it shuts down the system that
RETT should never be in cache (only executed once) so fix not necessary
in this case.
Any custom trap handlers may also have to be updated. To simplify that,
helper work around assembly code in macros are available in a separate
include file <libcpu/grlib-tn-0018.h>.
Close #4155.
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Close #4336.
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Update #4336.
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Update #4336.
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Run with stack alignment faults enabled under RTEMS_DEBUG to catch any
stack misalignments early. This makes it easier to track them down
should they ever occur.
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The Per_CPU_Control::isr_dispatch_disable is a 32-bit integer.
Close #4206.
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Clarify CPU_STACK_ALIGNMENT requirements in no_cpu port. Add static
assertion to enforce CPU_STACK_ALIGNMENT requirements.
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