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| author | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2021-03-04 08:12:47 +0100 |
|---|---|---|
| committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2021-03-05 15:06:18 +0100 |
| commit | 61d688bfcf191347af9b6a23f16176e6667d0bf5 (patch) | |
| tree | 45e58e2372162091d4b702c7fa577f28b48ec085 /cpukit/score/cpu | |
| parent | score: Ensure stack alignment requirement (diff) | |
| download | rtems-61d688bfcf191347af9b6a23f16176e6667d0bf5.tar.bz2 | |
aarch64: Fix context switch
The Per_CPU_Control::isr_dispatch_disable is a 32-bit integer.
Close #4206.
Diffstat (limited to 'cpukit/score/cpu')
| -rw-r--r-- | cpukit/score/cpu/aarch64/cpu_asm.S | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/cpukit/score/cpu/aarch64/cpu_asm.S b/cpukit/score/cpu/aarch64/cpu_asm.S index 6c4da04628..9e609e06bd 100644 --- a/cpukit/score/cpu/aarch64/cpu_asm.S +++ b/cpukit/score/cpu/aarch64/cpu_asm.S @@ -64,7 +64,7 @@ DEFINE_FUNCTION_AARCH64(_CPU_Context_switch) /* Start saving context */ GET_SELF_CPU_CONTROL reg_2 - ldr x3, [x2, #PER_CPU_ISR_DISPATCH_DISABLE] + ldr w3, [x2, #PER_CPU_ISR_DISPATCH_DISABLE] stp x19, x20, [x0] stp x21, x22, [x0, #0x10] @@ -109,7 +109,7 @@ DEFINE_FUNCTION_AARCH64(_CPU_Context_switch) msr TPIDR_EL0, x3 - str x4, [x2, #PER_CPU_ISR_DISPATCH_DISABLE] + str w4, [x2, #PER_CPU_ISR_DISPATCH_DISABLE] ldp x19, x20, [x1] ldp x21, x22, [x1, #0x10] |