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* score: Remove processor event broadcast/receiveSebastian Huber2021-07-288-103/+0
| | | | | | Remove _CPU_SMP_Processor_event_broadcast() and _CPU_SMP_Processor_event_receive(). These functions are hard to use since they are subject to the lost wake up problem.
* cpukit: occured -> occurredSebastian Huber2021-07-162-4/+4
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* sparc: Prefer RTEMS_FATAL_SOURCE_EXCEPTIONSebastian Huber2021-07-151-14/+0
| | | | | | Prefer RTEMS_FATAL_SOURCE_EXCEPTION over INTERNAL_ERROR_ILLEGAL_USE_OF_FLOATING_POINT_UNIT since the fatal code (rtems_exception_frame) provides more context.
* arm: For AArch32 use non-shareable memorySebastian Huber2021-06-291-2/+2
| | | | | | | | The Cortex-R52 does not support cache coherency and the shareable memory attribute. If a region is configured to be shareable, then it falls back to use non-cacheable memory. Update #4202.
* arm: Fix AARCH32_PMSA_ATTR_XN valueSebastian Huber2021-06-291-1/+1
| | | | Update #4202.
* arm: Fix AArch32 memory attribute definesSebastian Huber2021-06-291-4/+4
| | | | Update #4202.
* arm: Disable alignment check in PMSA initSebastian Huber2021-06-291-1/+1
| | | | | | | Disable the alignment check through SCTLR[A] in _AArch32_PMSA_Initialize(). Update #4202.
* sparc: Simplify trap table initializationSebastian Huber2021-06-243-54/+638
| | | | | | | | | | | | | | | Move _ISR_Handler() to a separate file since it is now only used if a handler is installed by _CPU_ISR_install_raw_handler(). Statically initialize the traps for external interrupts to use the new _SPARC_Interrupt_trap() which directly dispatches the interrupt handlers installed by rtems_interrupt_handler_install() via the BSP-provided _SPARC_Interrupt_dispatch(). Since the trap table is now fully statically initialized, there is no longer a dependency on the Cache Manager in the default configuration. Update #4458.
* sparc: Move FP frame offset defines to cpuimpl.hSebastian Huber2021-06-242-57/+57
| | | | | | This makes them usable in multiple files. Update #4458.
* sparc: More reliable bad trap handlingSebastian Huber2021-06-245-1/+513
| | | | | | | | | | | | | Statically initialize the trap table in start.S to jump to _SPARC_Bad_trap() for all unexpected traps. This enables a proper RTEMS fatal error handling right from the start. Do not rely on the stack and register settings which caused an unexpected trap. Use the ISR stack of the processor to do the fatal error handling. Save the full context which caused the trap. Fatal error handler may use it for error logging. Unify the _CPU_Exception_frame_print() implementations and move it to cpukit. Update #4459.
* sparc: Move ISR handler install routinesSebastian Huber2021-06-242-174/+201
| | | | | | | | Move _CPU_ISR_install_raw_handler() and _CPU_ISR_install_vector() to separate files. The goal is to make their use optional. Update #4458. Update #4459.
* score: Remove _CPU_Initialize_vectors()Sebastian Huber2021-06-2412-72/+0
| | | | | | | This CPU port macro was not used. Since the _ISR_Vector_table[] is statically allocated, CPU ports could initialize this table in _CPU_Initialize() if necessary. Remove _CPU_Initialize_vectors() to simplify the CPU port interface.
* cpu/armv7m: Fix initialization of MPU regionsChristian Mauderer2021-06-211-1/+1
| | | | | | | | | | | The write to RBAR didn't have the valid flag set. Therefore the write to RASR had an influence on the previously set region. That means for example that if Region 0 had been enabled but 1 should be disabled due to a size of 0, the previous code would have disabled region 0 instead. This patch fixes that behaviour. Close #4450
* cpu/armv7m: Avoid regions with negative sizeChristian Mauderer2021-06-211-1/+1
| | | | | | | Don't initialze regions that have a negative size (for example due to a wrong calculation). Update #4450
* arm: Fix parameter use in AARCH32_PMSA_MEM_ATTR()Sebastian Huber2021-06-161-1/+1
| | | | Update #4202.
* bsps/aarch64: Add MMU driver to relax alignmentKinsey Moore2021-05-271-16/+50
| | | | | | | | | | | | | | | Currently, the AArch64 BSPs have a hard time running on real hardware without building the toolchain and the bsps with -mstrict-align in multiple places. Configuring the MMU on these chips allows for unaligned memory accesses for non-device memory which avoids requiring strict alignment in the toolchain and in the BSPs themselves. In writing this driver, it was found that the synchronous exception handling code needed to be rewritten since it relied on clearing SCTLR_EL1 to avoid thread stack misalignments in RTEMS_DEBUG mode. This is now avoided by exactly preserving thread mode stack and flags and the new implementation is compatible with the draft information provided on the mailing list covering the Exception Management API.
* bsps/aarch64: Break out system registersKinsey Moore2021-05-271-0/+9985
| | | | | Break out system register definitions and accessors so that they're usable by other parts of RTEMS.
* score/aarch64: Align context validation frameKinsey Moore2021-05-261-11/+18
| | | | | | Ensure the stack remains aligned by keeping the context frame at a multiple of 16 bytes. This avoids stack alignment exceptions which occur when the stack pointer is not 16 byte aligned.
* score: Add _CPU_Context_switch_no_return()Sebastian Huber2021-05-188-4/+55
| | | | | | | | | | | The __builtin_unreachable() cannot be used with current GCC versions to tell the compiler that a function does not return to the caller, see: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99151 Add a no return variant of _CPU_Context_switch() to avoid generation of dead code in _Thread_Start_multitasking() if RTEMS was built with SMP support enabled.
* Remove superfluous <rtems/score/wkspace.h> includesSebastian Huber2021-04-208-8/+0
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* cpukit/aarch64: Restore ISR cookie bit maskKinsey Moore2021-04-191-13/+13
| | | | | | | The _CPU_ISR_Is_enabled() function operates on ISR cookies and so must mask off the appropriate status bits. This also fixes the naming of the parameters of the _CPU_ISR_* functions to indicate use of ISR cookies instead of interrupt enable/disable levels.
* cpukit/aarch64: Add ESR register decodingAlex White2021-04-061-10/+125
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* leon,tn-0018: work around GRLIB-TN-0018 errataDaniel Hellstrom2021-03-116-1/+105
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Overview ======== The errata is worked around in the kernel without requiring toolchain modifications. It is triggered the JMPL/RETT return from trap instruction sequence never generated by the compiler and. There are also other conditions that must must be true to trigger the errata, for example the instruction that the trap returns to has to be a JMPL instruction. The errata can only be triggered if certain data is corrected by ECC (inflicted by radiation), thus it can not be triggered under normal operation. For more information see: www.gaisler.com/notes Affected RTEMS target BSPs: * GR712RC * UT699 * UT700/699E The work around is enabled by defining __FIX_LEON3_TN0018 at build time. After applying the following GCC patch, GCC will set the define when compiling for an affected multilib: * GR712RC (-mcpu=leon3 -mfix-gr712rc) * UT700/UT699E (-mpcu=leon3 -mfix-ut700) * UT699 (-mcpu=leon -mfix-ut699) When building for another multilib and TN0018 is still required, it is possible to enable it on the RTEMS kernel configure line using the TARGET_CFLAGS (-D__FIX_LEON3FT_TN0018) or other by other means. The following GCC patch sets __FIX_LEON3FT_TN0018 for the affected RTEMS multilibs: --------- diff --git a/gcc/config/sparc/rtemself.h b/gcc/config/sparc/rtemself.h index 6570590..ddec98c 100644 --- a/gcc/config/sparc/rtemself.h +++ b/gcc/config/sparc/rtemself.h @@ -33,6 +33,8 @@ builtin_assert ("system=rtems"); \ if (sparc_fix_b2bst) \ builtin_define ("__FIX_LEON3FT_B2BST"); \ + if (sparc_fix_gr712rc || sparc_fix_ut700 || sparc_fix_ut699) \ + builtin_define ("__FIX_LEON3FT_TN0018"); \ } \ while (0) --------- Workaround Implementation ========================= In general there are two approaches that the workaround uses: A) avoid ECC restarting the RETT instruction B) avoid returning from trap to a JMPL instruction Where A) comes at a higher performance cost than B), so B) is used where posssible. B) can be achived for certain returns from trap handlers if trap entry is controlled by assembly, such as system calls. A) A special JMPL/RETT sequence where instruction cache is disabled temporarily to avoid RETT containing ECC errors, and reading of RETT source registers to "clean" them from incorrect ECC just before RETT is executed. B) The work around prevents JMPL after system calls (TA instruction) and modifies assembly code on return from traps jumping back to application code. Note that for some traps the trapped instruction is always re-executed and can therefore not trigger the errata, for example the SAVE instruction causing window overflow or an float instruction causing FPU disabled trap. RTEMS SPARC traps workaround implementation: NAME NOTE TRAP COMMENT * window overflow 1 - 0x05 always returns to a SAVE * window underflow 1 - 0x06 always returns to a RESTORE * interrupt traps 2 - 0x10..1f special rett sequence workaround * syscall 3 - 0x80 shutdown system - never returns * ABI flush windows 2 - 0x83 special rett sequence workaround * syscall_irqdis 4 - 0x89 * syscall_irqen 4 - 0x8A * syscall_irqdis_fp 1 - 0x8B always jumps back to FP instruction * syscall_lazy_fp_switch 5 - 0x04 A) jumps back to FP instruction, or to B) _Internal_error() starting with SAVE Notes: 1) no workaround needed because trap always returns to non-JMPL instruction 2) workaround implemented by special rett sequence 3) no workaround needed because system call never returns 4) workaround implemented by inserting NOP in system call generation. Thus fall into 1) when workaround is enabled and no trap handler fix needed. 5) trap handler branches into both 1) and returning to _Internal_error() which starts with a SAVE and besides since it shuts down the system that RETT should never be in cache (only executed once) so fix not necessary in this case. Any custom trap handlers may also have to be updated. To simplify that, helper work around assembly code in macros are available in a separate include file <libcpu/grlib-tn-0018.h>. Close #4155.
* sparc,leon: avoid triggering LEON3FT errata TN-0009Daniel Hellstrom2021-03-111-2/+3
| | | | Close #4336.
* sparc,leon: avoid triggering TN-0009 bad sequenceDaniel Hellstrom2021-03-111-1/+2
| | | | Update #4336.
* sparc: fix bad register alignment for 64 bit storeDaniel Hellstrom2021-03-111-1/+3
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* sparc: Remove sequences that the B2BST scan script warns aboutDaniel Cederman2021-03-112-3/+6
| | | | Update #4336.
* bsps/aarch64: RTEMS_DEBUG stack alignment faultsKinsey Moore2021-03-051-2/+8
| | | | | | Run with stack alignment faults enabled under RTEMS_DEBUG to catch any stack misalignments early. This makes it easier to track them down should they ever occur.
* score/aarch64: Fix interrupt level readsAlex White2021-03-052-3/+7
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* aarch64: Fix context switchSebastian Huber2021-03-051-2/+2
| | | | | | The Per_CPU_Control::isr_dispatch_disable is a 32-bit integer. Close #4206.
* score: Enforce CPU_STACK_ALIGNMENT requirementsSebastian Huber2021-03-0411-98/+8
| | | | | Clarify CPU_STACK_ALIGNMENT requirements in no_cpu port. Add static assertion to enforce CPU_STACK_ALIGNMENT requirements.
* nios2: Allow ISR nesting in dispatch variantSebastian Huber2021-02-012-173/+16
| | | | | | Rename _Nios2_ISR_Dispatch_with_shadow_non_preemptive() in _Nios2_ISR_Dispatch_with_shadow_register_set(). Remove _Nios2_ISR_Dispatch_with_shadow_preemptive().
* nios2: Optimize ISR dispatch variantSebastian Huber2021-02-011-42/+60
| | | | | Use _Thread_Do_dispatch() in _Nios2_ISR_Dispatch_with_shadow_non_preemptive().
* nios2: Use Per_CPU_Control::isr_dispatch_disableSebastian Huber2021-02-015-35/+23
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* nios2: Add TLS supportSebastian Huber2021-02-011-4/+15
| | | | Update #4214.
* nios2: Make _ISR_Is_in_progress() weakSebastian Huber2021-02-011-1/+1
| | | | This allows the BSP to override this function.
* nios2: Fix ISR dispatch variantsSebastian Huber2021-02-012-9/+7
| | | | | The thread dispatch disabled level moved to _Per_CPU_Information some time ago.
* Update header.amSebastian Huber2020-12-231-0/+2
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* arm: Add support for Arm PMSAv8-32Sebastian Huber2020-12-223-0/+568
| | | | Update #4202.
* arm: Add header file for AArch32 System RegistersSebastian Huber2020-12-221-0/+14657
| | | | Update #4202.
* arm: Optimize arm_interrupt_disable()Sebastian Huber2020-12-161-2/+11
| | | | Update #4202.
* cpu/armv7m: Fix table based init for ARMV7M_MPUChristian Mauderer2020-12-141-1/+7
| | | | | | | | Somehow the table index has been missing in the latest patch version. With that, the configuration for the first region has been applied multiple times. Update #4180
* cpukit/aarch64: Add explanation of exception flowKinsey Moore2020-12-102-3/+18
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* cpukit/aarch64: Use hex consistently for offsetsKinsey Moore2020-12-105-116/+116
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* arm: Support Armv8 in <rtems/score/arm.h>Sebastian Huber2020-12-101-11/+10
| | | | Update #4202.
* score/aarch64: Resolve warning in exception dumpKinsey Moore2020-11-241-2/+2
| | | | | This resolves a warning in the exception frame dump for AArch64 relating to a missized printf format specifier.
* cpu/armv7m: Add table based init for ARMV7M_MPUChristian Mauderer2020-11-201-0/+103
| | | | | | | Modify the MPU functions of the stm32h7 BSP to be table based and available for all ARMV7M BSPs. Update #4180
* score/aarch64: Size saved SP register for ABIKinsey Moore2020-11-131-1/+4
| | | | | This ensures that the saved SP register is sized appropriately depending on the chosen ABI and prevents a warning in the libmisc stack checker.
* sparc: Add SPARC_INTERRUPT_SOURCE_TO_TRAP()Sebastian Huber2020-11-061-0/+12
| | | | Update #4171.
* sparc: Add SPARC_INTERRUPT_TRAP_TO_SOURCE()Sebastian Huber2020-11-061-0/+17
| | | | Update #4171.
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