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* sparc: Move CPU counter implementationSebastian Huber2023-10-201-4/+2
| | | | | | Enable a BSP-specific CPU counter implementation. Update #4954.
* sparc: Fix stack corruptionSebastian Huber2023-10-121-1/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix a potential stack corruption in uniprocessor configurations during start multitasking. The system initialization uses the interrupt stack. A first level interrupt shall never interrupt a context which uses the interrupt stack. Such a use would lead to stack corruption and undefined system behaviour. Unfortunately, in uniprocessor configurations this was the case. Multiprocessing is started using _CPU_Context_restore(). The caller of this function (_Thread_Start_multitasking()) uses the interrupt stack. Later we have in cpukit/score/cpu/sparc/cpu_asm.S: mov %g1, %psr ! restore status register and ! **** ENABLE TRAPS **** ld [%o1 + G5_OFFSET], %g5 ! restore the global registers ld [%o1 + G7_OFFSET], %g7 ! Load thread specific ISR dispatch prevention flag ld [%o1 + ISR_DISPATCH_DISABLE_STACK_OFFSET], %o2 ! Store it to memory later to use the cycles ldd [%o1 + L0_OFFSET], %l0 ! restore the local registers ldd [%o1 + L2_OFFSET], %l2 ldd [%o1 + L4_OFFSET], %l4 ldd [%o1 + L6_OFFSET], %l6 ! Now restore thread specific ISR dispatch prevention flag st %o2, [%g6 + PER_CPU_ISR_DISPATCH_DISABLE] ldd [%o1 + I0_OFFSET], %i0 ! restore the input registers ldd [%o1 + I2_OFFSET], %i2 ldd [%o1 + I4_OFFSET], %i4 ldd [%o1 + I6_FP_OFFSET], %i6 ldd [%o1 + O6_SP_OFFSET], %o6 ! restore the output registers Between the ENABLE TRAPS and the restore of the output registers, we still use the stack of the caller and interrupts may be enabled. If an interrupt happens in this code block, the interrupt stack is concurrently used which may lead to a crash. Fix this by adding a new function _SPARC_Start_multiprocessing() for uniprocessor configurations. This function first sets the stack pointer to use the stack of the heir thread. Close #4955.
* Update company nameSebastian Huber2023-05-201-1/+1
| | | | | The embedded brains GmbH & Co. KG is the legal successor of embedded brains GmbH.
* score/cpu/sparc: Change license to BSD-2Joel Sherrill2022-02-281-3/+22
| | | | Updates #3053.
* sparc: Add workaround for GRLIB-TN-0011Sebastian Huber2021-11-261-0/+12
| | | | | | | | | | Affected components are the GR712RC, UT699, UT699E, UT700, and LEON3FT-RTAX. Strictly, the workaround is only necessary if the MMU is enabled. Use __FIX_LEON3FT_B2BST to enable the workaround. This is not 100% appropriate, but the best thing we can use to enable the workaround. Close #4551.
* sparc: Simplify trap table initializationSebastian Huber2021-06-241-52/+12
| | | | | | | | | | | | | | | Move _ISR_Handler() to a separate file since it is now only used if a handler is installed by _CPU_ISR_install_raw_handler(). Statically initialize the traps for external interrupts to use the new _SPARC_Interrupt_trap() which directly dispatches the interrupt handlers installed by rtems_interrupt_handler_install() via the BSP-provided _SPARC_Interrupt_dispatch(). Since the trap table is now fully statically initialized, there is no longer a dependency on the Cache Manager in the default configuration. Update #4458.
* sparc: Move FP frame offset defines to cpuimpl.hSebastian Huber2021-06-241-57/+36
| | | | | | This makes them usable in multiple files. Update #4458.
* score: Add _CPU_Context_switch_no_return()Sebastian Huber2021-05-181-0/+2
| | | | | | | | | | | The __builtin_unreachable() cannot be used with current GCC versions to tell the compiler that a function does not return to the caller, see: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99151 Add a no return variant of _CPU_Context_switch() to avoid generation of dead code in _Thread_Start_multitasking() if RTEMS was built with SMP support enabled.
* leon,tn-0018: work around GRLIB-TN-0018 errataDaniel Hellstrom2021-03-111-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Overview ======== The errata is worked around in the kernel without requiring toolchain modifications. It is triggered the JMPL/RETT return from trap instruction sequence never generated by the compiler and. There are also other conditions that must must be true to trigger the errata, for example the instruction that the trap returns to has to be a JMPL instruction. The errata can only be triggered if certain data is corrected by ECC (inflicted by radiation), thus it can not be triggered under normal operation. For more information see: www.gaisler.com/notes Affected RTEMS target BSPs: * GR712RC * UT699 * UT700/699E The work around is enabled by defining __FIX_LEON3_TN0018 at build time. After applying the following GCC patch, GCC will set the define when compiling for an affected multilib: * GR712RC (-mcpu=leon3 -mfix-gr712rc) * UT700/UT699E (-mpcu=leon3 -mfix-ut700) * UT699 (-mcpu=leon -mfix-ut699) When building for another multilib and TN0018 is still required, it is possible to enable it on the RTEMS kernel configure line using the TARGET_CFLAGS (-D__FIX_LEON3FT_TN0018) or other by other means. The following GCC patch sets __FIX_LEON3FT_TN0018 for the affected RTEMS multilibs: --------- diff --git a/gcc/config/sparc/rtemself.h b/gcc/config/sparc/rtemself.h index 6570590..ddec98c 100644 --- a/gcc/config/sparc/rtemself.h +++ b/gcc/config/sparc/rtemself.h @@ -33,6 +33,8 @@ builtin_assert ("system=rtems"); \ if (sparc_fix_b2bst) \ builtin_define ("__FIX_LEON3FT_B2BST"); \ + if (sparc_fix_gr712rc || sparc_fix_ut700 || sparc_fix_ut699) \ + builtin_define ("__FIX_LEON3FT_TN0018"); \ } \ while (0) --------- Workaround Implementation ========================= In general there are two approaches that the workaround uses: A) avoid ECC restarting the RETT instruction B) avoid returning from trap to a JMPL instruction Where A) comes at a higher performance cost than B), so B) is used where posssible. B) can be achived for certain returns from trap handlers if trap entry is controlled by assembly, such as system calls. A) A special JMPL/RETT sequence where instruction cache is disabled temporarily to avoid RETT containing ECC errors, and reading of RETT source registers to "clean" them from incorrect ECC just before RETT is executed. B) The work around prevents JMPL after system calls (TA instruction) and modifies assembly code on return from traps jumping back to application code. Note that for some traps the trapped instruction is always re-executed and can therefore not trigger the errata, for example the SAVE instruction causing window overflow or an float instruction causing FPU disabled trap. RTEMS SPARC traps workaround implementation: NAME NOTE TRAP COMMENT * window overflow 1 - 0x05 always returns to a SAVE * window underflow 1 - 0x06 always returns to a RESTORE * interrupt traps 2 - 0x10..1f special rett sequence workaround * syscall 3 - 0x80 shutdown system - never returns * ABI flush windows 2 - 0x83 special rett sequence workaround * syscall_irqdis 4 - 0x89 * syscall_irqen 4 - 0x8A * syscall_irqdis_fp 1 - 0x8B always jumps back to FP instruction * syscall_lazy_fp_switch 5 - 0x04 A) jumps back to FP instruction, or to B) _Internal_error() starting with SAVE Notes: 1) no workaround needed because trap always returns to non-JMPL instruction 2) workaround implemented by special rett sequence 3) no workaround needed because system call never returns 4) workaround implemented by inserting NOP in system call generation. Thus fall into 1) when workaround is enabled and no trap handler fix needed. 5) trap handler branches into both 1) and returning to _Internal_error() which starts with a SAVE and besides since it shuts down the system that RETT should never be in cache (only executed once) so fix not necessary in this case. Any custom trap handlers may also have to be updated. To simplify that, helper work around assembly code in macros are available in a separate include file <libcpu/grlib-tn-0018.h>. Close #4155.
* sparc,leon: avoid triggering LEON3FT errata TN-0009Daniel Hellstrom2021-03-111-2/+3
| | | | Close #4336.
* sparc: Remove sequences that the B2BST scan script warns aboutDaniel Cederman2021-03-111-2/+4
| | | | Update #4336.
* sparc: Fix mistakenly cleared PSR[EF] bit.Maksim E. Kozlov2019-06-071-1/+1
| | | | | The superfluously modified %l0 had no effect if the branch is not taken. This change clarifies the code.
* sparc: Move irq_asm.SSebastian Huber2018-04-201-0/+903
| | | | | | | | This file is BSP-independent. This patch is a part of the BSP source reorganization. Update #3285.
* sparc: Add lazy floating point switchSebastian Huber2017-07-251-127/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The SPARC ABI is a bit special with respect to the floating point context. The complete floating point context is volatile. Thus, from an ABI point of view nothing needs to be saved and restored during a context switch. Instead the floating point context must be saved and restored during interrupt processing. Historically, the deferred floating point switch was used for SPARC and the complete floating point context is saved and restored during a context switch to the new floating point unit owner. This is a bit dangerous since post-switch actions (e.g. signal handlers) and context switch extensions may silently corrupt the floating point context. The floating point unit is disabled for interrupt handlers. Thus, in case an interrupt handler uses the floating point unit then this will result in a trap (INTERNAL_ERROR_ILLEGAL_USE_OF_FLOATING_POINT_UNIT). In uniprocessor configurations, a lazy floating point context switch is used. In case an active floating point thread is interrupted (PSR[EF] == 1) and a thread dispatch is carried out, then this thread is registered as the floating point owner. When a floating point owner is present during a context switch, the floating point unit is disabled for the heir thread (PSR[EF] == 0). The floating point disabled trap checks that the use of the floating point unit is allowed and saves/restores the floating point context on demand. Update #3077.
* sparc: Rename SPARC_USE_SAFE_FP_SUPPORTSebastian Huber2017-07-251-1/+1
| | | | | | | Rename SPARC_USE_SAFE_FP_SUPPORT in SPARC_USE_SYNCHRONOUS_FP_SWITCH. Update comment. Update #3077.
* sparc: Add assembly workaround for LEON3FT B2BST errataDaniel Cederman2017-07-171-0/+22
| | | | | | | | | | | | | | | This patch adds NOP instructions to prevent instruction sequences that are sensitive to the LEON3FT B2BST errata. See GRLIB-TN-0009: "LEON3FT Stale Cache Entry After Store with Data Tag Parity Error" for more information. The sequences are only modified if __FIX_LEON3FT_B2BST is defined. The patch works in conjunction with the -mfix-ut700, -mfix-gr712rc, and -mfix-ut699 GCC flags that prevents the sensitive sequences from being generated. Update #3057.
* sparc: Add SPARC_USE_SAFE_FP_SUPPORTSebastian Huber2015-06-091-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | The SPARC ABI is a bit special with respect to the floating point context. The complete floating point context is volatile. Thus from an ABI point of view nothing needs to be saved and restored during a context switch. Instead the floating point context must be saved and restored during interrupt processing. Historically the deferred floating point switch is used for SPARC and the complete floating point context is saved and restored during a context switch to the new floating point unit owner. This is a bit dangerous since post-switch actions (e.g. signal handlers) and context switch extensions may silently corrupt the floating point context. The floating point unit is disabled for interrupt handlers. Thus in case an interrupt handler uses the floating point unit then this will result in a trap. On SMP configurations the deferred floating point switch is not supported in principle. So use here a safe floating point support. Safe means that the volatile floating point context is saved and restored around a thread dispatch issued during interrupt processing. Thus post-switch actions and context switch extensions may safely use the floating point unit. Update #2270.
* sparc: Remove superfluous FP enableSebastian Huber2015-05-301-22/+2
| | | | | | | The FP context save/restore makes only sense in the context of FP threads. Update #2270.
* sparc: Avoid new window for FP save/restoreSebastian Huber2015-05-301-54/+48
| | | | Update #2270.
* Change all references of rtems.com to rtems.org.Chris Johns2014-03-211-1/+1
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* sparc: Move _CPU_Context_switch(), etc.Sebastian Huber2013-08-091-224/+0
| | | | | | Move the _CPU_Context_switch(), _CPU_Context_restore() and _CPU_Context_switch_to_first_task_smp() code since the method to obtain the processor index is BSP specific.
* Remove All CVS Id Strings Possible Using a ScriptJoel Sherrill2012-05-111-2/+0
| | | | | | | | | | | | Script does what is expected and tries to do it as smartly as possible. + remove occurrences of two blank comment lines next to each other after Id string line removed. + remove entire comment blocks which only exited to contain CVS Ids + If the processing left a blank line at the top of a file, it was removed.
* 2011-10-07 Daniel Hellstrom <daniel@gaisler.com>Joel Sherrill2011-10-071-11/+11
| | | | | | | | | | | | | PR 1932/cpukit * cpu_asm.S: At some point the interrupt trap handler causes a window-overflow and the window overflow trap handler crashes when writing to 0. I found that this is because the WIM was bad, to the window overflow handler uses a uninitialized stack pointer in a window never used. * g3=CWP, not WIM * CWP is incremented by done_flushing no need doing that here also * I see no reason to create an additional stack frame (save) * Must turn off traps when updating WIM (maybe already done by caller?)
* 2011-03-16 Jennifer Averett <jennifer.averett@OARcorp.com>Joel Sherrill2011-03-161-523/+22
| | | | | | | | | | | | | | | | | | | | | | PR 1729/cpukit * configure.ac, sapi/include/confdefs.h, sapi/src/exinit.c, score/Makefile.am, score/preinstall.am, score/cpu/i386/rtems/score/cpu.h, score/cpu/sparc/cpu_asm.S, score/cpu/sparc/rtems/score/cpu.h, score/include/rtems/score/basedefs.h, score/include/rtems/score/context.h, score/include/rtems/score/percpu.h, score/src/percpu.c, score/src/thread.c, score/src/threadcreateidle.c: Add next step in SMP support. This adds an allocated array of the Per_CPU structures to support multiple cpus vs a single instance of the structure which is still used if SMP support is disabled. Configuration support is also added to explicitly enable or disable SMP. But SMP can only be enabled for the CPUs which will support it initially -- SPARC and i386. With the stub BSP support, a BSP can be run as a single core SMP system from an RTEMS data structure standpoint. * aclocal/check-smp.m4, aclocal/enable-smp.m4, score/include/rtems/bspsmp.h, score/include/rtems/score/smplock.h, score/src/smp.c, score/src/smplock.c: New files.
* 2010-06-28 Joel Sherrill <joel.sherrill@oarcorp.com>Joel Sherrill2010-06-291-48/+21
| | | | | | | | PR 1573/cpukit * cpu_asm.S, rtems/score/cpu.h: Add a per cpu data structure which contains the information required by RTEMS for each CPU core. This encapsulates information such as thread executing, heir, idle and dispatch needed.
* 2010-03-27 Joel Sherrill <joel.sherrill@oarcorp.com>Joel Sherrill2010-03-271-0/+4
| | | | * cpu.c, cpu_asm.S: Add include of config.h
* Whitespace removal.Ralf Corsepius2009-12-021-24/+24
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* 2009-03-12 Joel Sherrill <joel.sherrill@OARcorp.com>Joel Sherrill2009-03-121-4/+4
| | | | | | | | PR 1385/cpukit * cpu_asm.S: When the type rtems_boolean was switched to the C99 bool, the size changed from 4 bytes to 1 byte. The interrupt dispatching code accesses two boolean variables for scheduling purposes and the assembly implementations of this code did not get updated.
* Fix date.Joel Sherrill2008-05-061-1/+1
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* 2007-05-10 Joel Sherrill <joel.sherrill@OARcorp.com>Joel Sherrill2007-05-101-5/+75
| | | | | | | | PR 1237/rtems * cpu.c, cpu_asm.S, rtems/score/cpu.h: Add logic to prevent stack creep when interrupts occur at a sufficient rate that the interrupted thread never gets to clean its stack. This patch ensures that an interrupted thread will not nest ISR dispatches on its stack.
* 2006-11-14 Jiri Gaisler <jiri@gaisler.com>Joel Sherrill2006-11-141-0/+5
| | | | * cpu_asm.S: Properly support synchronous traps.
* 2004-04-01 Ralf Corsepius <ralf_corsepius@rtems.org>Ralf Corsepius2004-04-011-1/+1
| | | | * cpu_asm.S: Include <rtems/asm.h> instead of <asm.h>.
* 2004-02-26 Andreas Karlsson <andreas.karlsson@space.se>Joel Sherrill2004-02-261-0/+11
| | | | | * cpu_asm.S: Close window while restoring interrupted task state which resulted in CWP corruption.
* 2003-09-04 Joel Sherrill <joel@OARcorp.com>Joel Sherrill2003-09-041-1/+1
| | | | | * cpu.c, cpu_asm.S, rtems/score/cpu.h, rtems/score/sparc.h, rtems/score/types.h: URL for license changed.
* 2001-09-27 Jiri Gaisler <jiri@gaisler.com>Joel Sherrill2001-09-271-4/+4
| | | | | | * cpu_asm.S: Small patch to fix a bug in the rtems sparc port. The bug has been there all the time, but only hits the leon bsp since the leon cpu has a 5-stage pipeline (erc32 has 4 stages).
* 2001-01-03 Joel Sherrill <joel@OARcorp.com>Joel Sherrill2001-01-031-1/+1
| | | | | | * rtems/score/cpu.h: Added _CPU_Initialize_vectors(). * cpu_asm.S: Modify to properly dereference _ISR_Vector_table now that it is dynamically allocated.
* 2000-11-21 Jiri Gaisler <jgais@ws.estec.esa.nl>Joel Sherrill2000-11-211-3/+10
| | | | * cpu_asm.S: Fix for CPUs with FPU revision B or C.
* Reworked score/cpu/sparc so it can be safely compiled multilib. AllJoel Sherrill2000-07-111-7/+0
| | | | | | routines and structures that require CPU model specific information are now in libcpu. This primarily required moving erc32 specific information from score/cpu files to libcpu/sparc and the erc32 BSP.
* Updated copyright notice.Joel Sherrill1999-11-171-2/+1
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* Patch from Jiri Gaisler <jgais@ws.estec.esa.nl>:Joel Sherrill1999-07-091-3/+71
| | | | | | + interrupt masking correction + FPU rev.B workaround + minor erc32 related fixes
* Patch from Jiri Gaisler <jgais@ce.chalmers.se>:Joel Sherrill1999-01-191-0/+2
| | | | | | | | getting the spurious trap handling to work required a couple more fixes - I have attached a patch against rtems-4.0.0 with the necessary changes. I also added functionality so that the address of the trapped instruction is reported and in case of a data access error, the data address is also reported.
* Patch from Ralf Corsepius <corsepiu@faw.uni-ulm.de> to rename allJoel Sherrill1998-12-141-0/+726
.s files to .S in conformance with GNU conventions. This is a minor step along the way to supporting automake.
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