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* Update company nameSebastian Huber2023-05-201-1/+1
| | | | | The embedded brains GmbH & Co. KG is the legal successor of embedded brains GmbH.
* cpukit/: Scripted embedded brains header file clean upJoel Sherrill2022-03-101-6/+0
| | | | Updates #4625.
* score/cpu/arm: Change license to BSD-2Joel Sherrill2022-02-281-3/+22
| | | | Updates #3053.
* arm: Optimize interrupt handlingSebastian Huber2022-01-171-0/+39
| | | | | Use the SRS (Store Return State) instruction if available. This considerably simplifies the context save and restore.
* arm: Fix stack alignment during interrupt handlingSebastian Huber2022-01-171-10/+23
| | | | | | | | | | | On a public interface, the stack pointer must be aligned on an 8-byte boundary. However, it may temporarily be only aligned on a 4-byte boundary. The interrupt handling code must ensure that the stack pointer is properly aligned before it calls a function. See also: https://developer.arm.com/documentation/den0013/d/Interrupt-Handling/External-interrupt-requests/Nested-interrupt-handling Update #4579.
* arm: Avoid duplicate move from CPSRSebastian Huber2022-01-171-4/+3
| | | | Update #4579.
* arm: Rework per-CPU control in interrupt handlingSebastian Huber2022-01-151-56/+46
| | | | | | | | Use volatile register r0 for the per-CPU control of the current processor instead of the non-volatile register r7. This enables the use of r7 in a follow up patch. Do the interrupt handling in ARM mode. Update #4579.
* arm: Use push/pop instructions for readabilitySebastian Huber2022-01-151-11/+11
| | | | Update #4579.
* score: Add ARM CPU architecture groupSebastian Huber2019-03-261-1/+1
| | | | Update #3706.
* score: Rename ScoreCPU Doxygen groupSebastian Huber2019-03-261-1/+1
| | | | Update #3706.
* arm: Fix profiling support of Thumb-1 targetsSebastian Huber2017-05-231-1/+3
| | | | Update #2751.
* arm: Fix _ARMV4_Exception_interruptSebastian Huber2016-11-231-1/+1
| | | | | | | Use the right register to determine if a thread dispatch is allowed and necessary. Update #2751.
* arm: Fix Thumb-1 targetsSebastian Huber2016-11-211-10/+10
| | | | | | | We cannot use the MRS or MSR instructions in Thumb-1 mode. Stay in ARM mode for the Thumb-1 targets during interrupt low-level processing. Update #2751.
* arm: Use Per_CPU_Control::isr_dispatch_disableSebastian Huber2016-11-181-25/+60
| | | | Update #2751.
* arm: Simplify _ARMV4_Exception_interruptSebastian Huber2016-11-181-18/+22
| | | | | Move profiling code closer to bsp_interrupt_disable() to allow re-use of r9 later.
* arm: Use local labelsSebastian Huber2016-11-181-9/+9
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* arm: Use TPIDRPRW for current per-CPU controlSebastian Huber2016-11-181-1/+1
| | | | | | Use the previously unused TPIDRPRW register to get the per-CPU control of the current processor. This avoids instructions in GET_SELF_CPU_CONTROL which are not available in Thumb mode.
* Fix interrupt epilogue for ARMv7-AR and PowerPCSebastian Huber2015-11-121-0/+27
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* arm: Add support for FPv4-SP floating point unitSebastian Huber2014-08-121-4/+8
| | | | | This floating point unit is available in Cortex-M4 processors and defined by ARMv7-M. This adds basic support for other VFP-D16 variants.
* score: PR2183: Fix context switch on SMPSebastian Huber2014-07-041-12/+0
| | | | | | | | Fix context switch on SMP for ARM, PowerPC and SPARC. Atomically test and set the is executing indicator of the heir context to ensure that at most one processor uses the heir context. Break the busy wait loop also due to heir updates.
* Change all references of rtems.com to rtems.org.Chris Johns2014-03-211-1/+1
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* arm: Add support for interrupt profilingSebastian Huber2014-03-141-0/+20
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* arm: Fix stack alignment in interrupt handlerSebastian Huber2014-03-101-29/+19
| | | | | | According to AAPCS, section 5.2.1.2, "Stack constraints at a public interface" the stack must be 8 byte aligned. This was not the case during interrupt processing.
* arm: Per-CPU thread dispatch disableSebastian Huber2013-08-091-51/+25
| | | | Interrupt support for per-CPU thread dispatch disable level.
* smp: Add ARM supportSebastian Huber2013-05-311-2/+33
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* arm: Fix CPSR and SPSR accessSebastian Huber2013-05-271-6/+6
| | | | | | | | | | | | | | | The GNU assembler translates for example a msr spsr, rN into msr SPSR_fc, rN This would update only a subset of the register and leads to an incomplete exceptions restore sequence resulting in system corruption. Correct is this: msr SPSR_fsxc, rN
* arm: Support VFP-D32 and NeonSebastian Huber2013-05-101-6/+33
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* arm: Rename arm_exc_interrupt()Sebastian Huber2013-01-071-2/+2
| | | | Rename arm_exc_interrupt() to _ARMV4_Exception_interrupt().
* 2011-09-24 Sebastian Huber <sebastian.huber@embedded-brains.de>Sebastian Huber2011-09-241-0/+4
| | | | | | | | | | | | | | | | | | * rtems/score/armv7m.h, armv7m-context-initialize.c, armv7m-context-restore.c, armv7m-context-switch.c, armv7m-exception-handler-get.c, armv7m-exception-handler-set.c, armv7m-exception-priority-get.c, armv7m-exception-priority-set.c, armv7m-initialize.c, armv7m-isr-dispatch.c, armv7m-isr-enter-leave.c, armv7m-isr-level-get.c, armv7m-isr-level-set.c, armv7m-isr-vector-install.c, armv7m-multitasking-start-stop.c: New files. * Makefile.am, preinstall.am: Reflect changes above. * rtems/score/arm.h: Define ARM_MULTILIB_ARCH_V4 and ARM_MULTILIB_ARCH_V7M. * rtems/score/cpu.h, cpu_asm.S, cpu.c, arm_exc_abort.S, arm_exc_handler_high.c, arm_exc_handler_low.S, arm_exc_interrupt.S: Define CPU_HAS_HARDWARE_INTERRUPT_STACK to FALSE. Use ARM_MULTILIB_ARCH_V4 and ARM_MULTILIB_ARCH_V7M.
* 2010-06-28 Joel Sherrill <joel.sherrill@oarcorp.com>Joel Sherrill2010-06-291-15/+4
| | | | | | | PR 1573/cpukit * arm_exc_interrupt.S: Add a per cpu data structure which contains the information required by RTEMS for each CPU core. This encapsulates information such as thread executing, heir, idle and dispatch needed.
* add/adapt documentationThomas Doerfler2010-04-081-1/+1
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* 2010-03-27 Joel Sherrill <joel.sherrill@oarcorp.com>Joel Sherrill2010-03-271-0/+4
| | | | | * arm_exc_abort.S, arm_exc_handler_high.c, arm_exc_handler_low.S, arm_exc_interrupt.S, cpu.c, cpu_asm.S: Add include of config.h
* add support for lpc32xxThomas Doerfler2010-01-121-16/+4
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* add support for ARM11, reimplement nested interruptsThomas Doerfler2009-12-151-149/+116
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* adding lpc24xx BSP partsThomas Doerfler2009-07-171-0/+229
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