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* arm: Move _CPU_ISR_install_vector()Sebastian Huber2024-03-202-27/+76
| | | | The use of this function is optional. Newer BSPs do not use it.
* arm: Use a valid signed integer constantSebastian Huber2023-09-261-1/+1
| | | | Enumerators are restricted to signed integers in some C standards.
* score: Add _CPU_Get_TLS_thread_pointer()Sebastian Huber2023-09-151-0/+7
| | | | | | | | Add _CPU_Get_TLS_thread_pointer() to get the thread pointer which is used to get the address of thread-local storage objects associated with a thread. Update #4920.
* score: Fix TLS support for some code modelsSebastian Huber2023-09-151-1/+1
| | | | | | | | Store symbols with an arbitrary absolute address such as _TLS_Size, _TLS_Alignment, _TLS_Data_size, and _TLS_BSS_size in an object to avoid issues with some code models. Update #4953.
* arm: Fix cache support for ARM926EJ-SSebastian Huber2023-08-101-4/+22
| | | | | | | The ARM926EJ-S is an ARMv5T architecture processor and lacks some features of ARMv6 processors such as the ARM1176JZF-S. Close #4940.
* score/arm: improve printed exception information for Cortex-Mx CPUsKarel Gardas2023-07-142-2/+154
| | | | Sponsored-By: Precidata
* score: Remove CPU port specific cpuatomic.hSebastian Huber2023-06-121-33/+0
| | | | | All CPU ports used the same <rtems/score/cpustdatomic.h> header file to provide the atomic operations. Remove the header file indirection.
* arm: Use RTEMS_XCONCAT()Sebastian Huber2023-05-261-4/+2
| | | | Prefer macros with a proper namespace.
* arm: Improve Doxygen file commentsSebastian Huber2023-05-2629-35/+165
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* Update company nameSebastian Huber2023-05-2023-23/+23
| | | | | The embedded brains GmbH & Co. KG is the legal successor of embedded brains GmbH.
* score/arm: enhance ARMV7M MPU setup with capability to set control registerKarel Gardas2023-03-161-1/+2
| | | | | | | Due to API change, the patch also fixes affected BSPs and uses value provided by MPU CTRL spec option there. Sponsored-By: Precidata
* arm: Enable thread ID register for ARMv6Sebastian Huber2023-01-031-1/+2
| | | | Close #4759.
* arm: Fix Armv7-M TLS supportSebastian Huber2022-11-101-1/+1
| | | | | | | Set the thread ID register in the CPU context. Update #3835. Close #4753.
* score: Add CPU_THREAD_LOCAL_STORAGE_VARIANTSebastian Huber2022-10-146-26/+17
| | | | Update #3835.
* Do not use RTEMS_INLINE_ROUTINESebastian Huber2022-09-192-4/+4
| | | | | | | Directly use "static inline" which is available in C99 and later. This brings the RTEMS implementation closer to standard C. Close #3935.
* score: Remove _CPU_Counter_difference()Sebastian Huber2022-09-091-8/+0
| | | | | | | All CPU ports used the same _CPU_Counter_difference() implementation. Remove this CPU port interface and mandate a monotonically increasing CPU counter. Close #3456.
* score: Add _CPU_Use_thread_local_storage()Sebastian Huber2022-07-041-0/+13
| | | | | | | | | | | | At some point during system initialization, the idle threads are created. Afterwards, the boot processor basically executes within the context of an idle thread with thread dispatching disabled. On some architectures, the thread-local storage area of the associated thread must be set in dedicated processor registers. Add the new CPU port function to do this: void _CPU_Use_thread_local_storage( const Context_Control *context ) Close #4672.
* score/cpu: Silence ARM and AARCH64 GCC 12 false trigger array warningChris Johns2022-06-151-1/+4
| | | | | | | | | | | | The false trigger is covered in: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99578 GCC 11 and 12 has been patched for constant pointer casts above 4K. This code casts a constant pointer within the first 4K page. As a result the patch disables the warning. Updates #4662
* arm: Fix PMSA regions for contiguous sectionsSebastian Huber2022-06-081-4/+4
| | | | | | | | | | Sections with identical attributes may be contiguous with a respective begin and end address which is not on a minimum region boundary. The begin address is aligned down to the region base address. The end address is aligned up to the region end address. Account for this in the check for contiguous sections. Update #4202.
* arm: Fix PMSA region mapping with 0x0 end addressSebastian Huber2022-06-081-1/+1
| | | | | | | | A section may span up to the end of the address range. In this case the end address is zero. Use the base address to check if a region should be before another region. Update #4202.
* arm: Fix typoSebastian Huber2022-06-031-2/+2
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* arm: Fix PMSA section to region mappingSebastian Huber2022-03-111-22/+33
| | | | | Fix move of regions. Allow sections to be contained in a region (may happen due to region alignment).
* arm: Add _AArch32_PMSA_Map_sections_to_regions()Sebastian Huber2022-03-112-20/+90
| | | | This simplifies unit testing.
* cpukit/: Scripted embedded brains header file clean upJoel Sherrill2022-03-1029-174/+1
| | | | Updates #4625.
* SMP: Fix start multitasking for some targetsSebastian Huber2022-03-092-0/+16
| | | | | | | | | | | | | The previous SMP multitasking start assumed that the initial heir thread of a processor starts execution in _Thread_Handler(). The _Thread_Handler() sets the interrupt state explicitly by _ISR_Set_level() before it calls the thread entry. Under certain timing conditions, processors may perform an initial context switch to a thread which already executes its thread body (see smptests/smpstart01). In this case, interrupts are disabled after the context switch on targets which do not save/restore the interrupt state during a context switch (aarch64, arm, and riscv). Close #4627.
* score/cpu/arm: Change license to BSD-2Joel Sherrill2022-02-2838-115/+836
| | | | Updates #3053.
* arm: Optimize interrupt handlingSebastian Huber2022-01-173-0/+53
| | | | | Use the SRS (Store Return State) instruction if available. This considerably simplifies the context save and restore.
* arm: Fix stack alignment during interrupt handlingSebastian Huber2022-01-171-10/+23
| | | | | | | | | | | On a public interface, the stack pointer must be aligned on an 8-byte boundary. However, it may temporarily be only aligned on a 4-byte boundary. The interrupt handling code must ensure that the stack pointer is properly aligned before it calls a function. See also: https://developer.arm.com/documentation/den0013/d/Interrupt-Handling/External-interrupt-requests/Nested-interrupt-handling Update #4579.
* arm: Avoid duplicate move from CPSRSebastian Huber2022-01-171-4/+3
| | | | Update #4579.
* arm: Rework per-CPU control in interrupt handlingSebastian Huber2022-01-151-56/+46
| | | | | | | | Use volatile register r0 for the per-CPU control of the current processor instead of the non-volatile register r7. This enables the use of r7 in a follow up patch. Do the interrupt handling in ARM mode. Update #4579.
* arm: Use push/pop instructions for readabilitySebastian Huber2022-01-151-11/+11
| | | | Update #4579.
* arm: Add AARCH32_PMSA_DATA_READ_WRITE_DEFAULTSebastian Huber2021-11-301-8/+28
| | | | | | | Add default memory attributes for read-write data. The actual attributes depend on the RTEMS_SMP build option. Update #4202.
* arm: Fix AARCH32_PMSA_DATA_READ_WRITE_CACHEDSebastian Huber2021-11-301-1/+1
| | | | | | | Fix definition of AARCH32_PMSA_DATA_READ_WRITE_CACHED. Since AARCH32_PMSA_ATTR_AP_EL1_RW_EL0_NO is zero, this fix is only cosmetic. Update #4202.
* cpukit: Consistize OAR copyright headersKinsey Moore2021-11-221-1/+1
| | | | | | These two OAR copyright headers are the only two in the codebase with a format that differs from the typical OAR copyright header. This makes all of the OAR copyright headers consistent.
* build: Remove old build systemSebastian Huber2021-09-211-14/+0
| | | | | Close #3250. Close #4081.
* score: Canonicalize _CPU_Fatal_halt()Sebastian Huber2021-07-283-15/+20
| | | | | | | | Move _CPU_Fatal_halt() declaration to <rtems/score/cpuimpl.h> and make sure it is a proper declaration of a function which does not return. Fix the type of the error code. If necessary, add the implementation to cpu.c. Implementing _CPU_Fatal_halt() as a function makes it possible to wrap this function for example to fully test _Terminate().
* score: Remove processor event broadcast/receiveSebastian Huber2021-07-281-12/+0
| | | | | | Remove _CPU_SMP_Processor_event_broadcast() and _CPU_SMP_Processor_event_receive(). These functions are hard to use since they are subject to the lost wake up problem.
* arm: For AArch32 use non-shareable memorySebastian Huber2021-06-291-2/+2
| | | | | | | | The Cortex-R52 does not support cache coherency and the shareable memory attribute. If a region is configured to be shareable, then it falls back to use non-cacheable memory. Update #4202.
* arm: Fix AARCH32_PMSA_ATTR_XN valueSebastian Huber2021-06-291-1/+1
| | | | Update #4202.
* arm: Fix AArch32 memory attribute definesSebastian Huber2021-06-291-4/+4
| | | | Update #4202.
* arm: Disable alignment check in PMSA initSebastian Huber2021-06-291-1/+1
| | | | | | | Disable the alignment check through SCTLR[A] in _AArch32_PMSA_Initialize(). Update #4202.
* cpu/armv7m: Fix initialization of MPU regionsChristian Mauderer2021-06-211-1/+1
| | | | | | | | | | | The write to RBAR didn't have the valid flag set. Therefore the write to RASR had an influence on the previously set region. That means for example that if Region 0 had been enabled but 1 should be disabled due to a size of 0, the previous code would have disabled region 0 instead. This patch fixes that behaviour. Close #4450
* cpu/armv7m: Avoid regions with negative sizeChristian Mauderer2021-06-211-1/+1
| | | | | | | Don't initialze regions that have a negative size (for example due to a wrong calculation). Update #4450
* arm: Fix parameter use in AARCH32_PMSA_MEM_ATTR()Sebastian Huber2021-06-161-1/+1
| | | | Update #4202.
* score: Add _CPU_Context_switch_no_return()Sebastian Huber2021-05-182-0/+8
| | | | | | | | | | | The __builtin_unreachable() cannot be used with current GCC versions to tell the compiler that a function does not return to the caller, see: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99151 Add a no return variant of _CPU_Context_switch() to avoid generation of dead code in _Thread_Start_multitasking() if RTEMS was built with SMP support enabled.
* Update header.amSebastian Huber2020-12-231-0/+2
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* arm: Add support for Arm PMSAv8-32Sebastian Huber2020-12-223-0/+568
| | | | Update #4202.
* arm: Add header file for AArch32 System RegistersSebastian Huber2020-12-221-0/+14657
| | | | Update #4202.
* arm: Optimize arm_interrupt_disable()Sebastian Huber2020-12-161-2/+11
| | | | Update #4202.
* cpu/armv7m: Fix table based init for ARMV7M_MPUChristian Mauderer2020-12-141-1/+7
| | | | | | | | Somehow the table index has been missing in the latest patch version. With that, the configuration for the first region has been applied multiple times. Update #4180
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