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* bsps/powerpc: Move basic support to bspsSebastian Huber2018-03-191-595/+0
| | | | | | This patch is a part of the BSP source reorganization. Update #3285.
* Add PowerPC paravirtualization supportJoel Sherrill2018-03-131-0/+16
| | | | | | | | | Cannot read or write MSR when executing in user mode. This is used when RTEMS_PARAVIRT is defined. Provide alternate methods to disable/enable interrupts Closes #3306.
* powerpc: Add 64-bit context/interrupt supportSebastian Huber2017-08-221-16/+21
| | | | Update #3082.
* Simplify TLS support in context switchSebastian Huber2017-06-091-1/+0
| | | | | | There is no need to save the thread pointer in _CPU_Context_switch() since it is a thread invariant. It is initialized once in _CPU_Context_Initialize().
* powerpc: Optimize AltiVec context switchSebastian Huber2017-03-071-2/+0
| | | | | | Use r8 instead of r5 to slightly optimize _CPU_Context_switch(). It is not a big deal, however, we already assume r12 is used by _CPU_Context_switch(). Treat r5 the in same way.
* powerpc: Use Per_CPU_Control::isr_dispatch_disableSebastian Huber2016-11-181-1/+7
| | | | Update #2751.
* score: Allow interrupts during thread dispatchSebastian Huber2016-11-181-12/+17
| | | | | | | | | Use a processor-specific interrupt frame during context switches in case the executing thread is longer executes on the processor and the heir thread is about to start execution. During this period we must not use a thread stack for interrupt processing. Update #2809.
* powerpc: Fix SMP context switchSebastian Huber2016-09-081-61/+62
| | | | | | We need the unmodified r4 for get_potential_new_heir. This partially reverts commit 8d785f72d9610fb80a65d7848404f0f7507e026c.
* bsps/powerpc: Fix AtliVec context switchSebastian Huber2016-07-191-62/+62
| | | | | | | Properly pass the stack aligned context to _CPU_Context_switch_altivec() since _CPU_altivec_ctxt_off defined via ppc_context. Close #2761.
* SMP: Fix and optimize thread dispatchingSebastian Huber2015-09-281-14/+11
| | | | | | | | According to the C11 and C++11 memory models only a read-modify-write operation guarantees that we read the last value written in modification order. Avoid the sequential consistent thread fence and instead use the inter-processor interrupt to set the thread dispatch necessary indicator.
* powerpc: AltiVec and FPU context supportSebastian Huber2015-01-131-3/+127
| | | | | | | | | | | Add AltiVec and FPU support to the Context_Control in case we use the e6500 multilib. Add PPC_MULTILIB_ALTIVEC and PPC_MULTILIB_FPU multilib defines. Add non-volatile AltiVec and FPU context to Context_Control. Add save/restore of non-volatile AltiVec and FPU to _CPU_Context_switch(). Add save/restore of volatile AltiVec and FPU context to the exception code. Adjust data cache optimizations for the new context and cache line size.
* powerpc: Use PPC_HAS_FPUSebastian Huber2015-01-091-6/+6
| | | | Provide floating point context support only if PPC_HAS_FPU == 1.
* powerpc: Set PPC_DEFAULT_CACHE_LINE_SIZE for e6500Sebastian Huber2015-01-091-15/+11
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* score: PR2183: Fix context switch on SMPSebastian Huber2014-07-041-50/+90
| | | | | | | | Fix context switch on SMP for ARM, PowerPC and SPARC. Atomically test and set the is executing indicator of the heir context to ensure that at most one processor uses the heir context. Break the busy wait loop also due to heir updates.
* score: Fix CPU context usage on SMPSebastian Huber2014-05-081-8/+6
| | | | | | | | | | We must not alter the is executing indicator in _CPU_Context_Initialize() since this would cause an invalid state during a self restart. The is executing indicator must be valid at creation time since otherwise _Thread_Kill_zombies() uses an undefined value for not started threads. This could result in a system life lock.
* score: Implement forced thread migrationSebastian Huber2014-05-071-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current implementation of task migration in RTEMS has some implications with respect to the interrupt latency. It is crucial to preserve the system invariant that a task can execute on at most one processor in the system at a time. This is accomplished with a boolean indicator in the task context. The processor architecture specific low-level task context switch code will mark that a task context is no longer executing and waits that the heir context stopped execution before it restores the heir context and resumes execution of the heir task. So there is one point in time in which a processor is without a task. This is essential to avoid cyclic dependencies in case multiple tasks migrate at once. Otherwise some supervising entity is necessary to prevent life-locks. Such a global supervisor would lead to scalability problems so this approach is not used. Currently the thread dispatch is performed with interrupts disabled. So in case the heir task is currently executing on another processor then this prolongs the time of disabled interrupts since one processor has to wait for another processor to make progress. It is difficult to avoid this issue with the interrupt latency since interrupts normally store the context of the interrupted task on its stack. In case a task is marked as not executing we must not use its task stack to store such an interrupt context. We cannot use the heir stack before it stopped execution on another processor. So if we enable interrupts during this transition we have to provide an alternative task independent stack for this time frame. This issue needs further investigation.
* Change all references of rtems.com to rtems.org.Chris Johns2014-03-211-1/+1
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* bsps/powerpc: Unconditionally clear reservationsSebastian Huber2013-12-031-7/+8
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* powerpc: Add r2 to CPU contextSebastian Huber2013-11-181-1/+5
| | | | The r2 may be used for thread-local storage.
* smp: Fix PowerPC context switchSebastian Huber2013-06-071-1/+1
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* powerpc: Simplify context switchSebastian Huber2012-06-041-264/+90
| | | | | | | | | | | | | | | | | | | PowerPC cores with the SPE (Signal Processing Extension) have 64-bit general-purpose registers. The SPE context switch code has been merged with the standard context switch code. The context switch may use cache operations to increase the performance. It will be ensured that the context is 32-byte aligned (PPC_DEFAULT_CACHE_LINE_SIZE). This increases the overall memory size of the context area in the thread control block slightly. The general-purpose registers GPR2 and GPR13 are no longer part of the context. The BSP must initialize these registers during startup (usually initialized by the __eabi() function). The new BSP option BSP_USE_DATA_CACHE_BLOCK_TOUCH can be used to enable the dcbt instruction in the context switch. The new BSP option BSP_USE_SYNC_IN_CONTEXT_SWITCH can be used to enable sync and isync instructions in the context switch. This should be not necessary in most cases.
* Remove All CVS Id Strings Possible Using a ScriptJoel Sherrill2012-05-111-3/+0
| | | | | | | | | | | | Script does what is expected and tries to do it as smartly as possible. + remove occurrences of two blank comment lines next to each other after Id string line removed. + remove entire comment blocks which only exited to contain CVS Ids + If the processing left a blank line at the top of a file, it was removed.
* 2011-07-21 Sebastian Huber <sebastian.huber@embedded-brains.de>Sebastian Huber2011-07-211-30/+139
| | | | | | | | | | | | PR 1799/bsps * new-exceptions/bspsupport/ppc_exc_async_normal.S: New file. * new-exceptions/cpu.c, new-exceptions/cpu_asm.S, new-exceptions/bspsupport/ppc_exc_asm_macros.h, new-exceptions/bspsupport/ppc_exc_global_handler.c, new-exceptions/bspsupport/ppc_exc_prologue.c, new-exceptions/bspsupport/vectors.h: Added support for SPE. * configure.ac, preinstall.am, Makefile.am: Added support for qoriq BSPs.
* 2011-06-07 Sebastian Huber <sebastian.huber@embedded-brains.de>Sebastian Huber2011-06-071-9/+9
| | | | | * new-exceptions/cpu_asm.S: Use BSP_DATA_CACHE_ENABLED instead of PPC_USE_DATA_CACHE.
* 2009-12-01 Till Straumann <strauman@slac.stanford.edu>Till Straumann2009-12-021-32/+50
| | | | | | | | | * new-exceptions/cpu.c, new-exceptions/cpu_asm.S, new-exceptions/bspsupport/ppc_exc_asm_macros.h, new-exceptions/bspsupport/ppc_exc_initialize.c, new-exceptions/bspsupport/vectors.h: Added AltiVec support (save/restore volatile vregs across exceptions).
* FP context switch may be called from environment with noTill Straumann2006-06-191-0/+29
| | | | | FPU available (ISR, int-only task) - switch FPU on for the switch and restore MSR_FP after it's done.
* 2005-11-21 Till Straumann <strauman@slac.stanford.edu>Till Straumann2005-11-221-0/+2
| | | | | | | * new-exceptions/cpu_asm.S: the book says a context synchronizing instruction (isync) is necessary after flipping certain bits (e.g, MSR_FP) in msr -- since this could happen as part of a context switch I added 'isync'.
* 2005-02-14 Ralf Corsepius <ralf.corsepius@rtems.org>Ralf Corsepius2005-02-141-0/+1
| | | | * cpu.c, cpu_asm.S, irq_stub.S: #include <rtems/powerpc/powerpc.h>.
* Remove duplicate white lines.Ralf Corsepius2004-04-211-1/+0
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* Remove stray white spaces.Ralf Corsepius2004-04-211-6/+6
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* Remove stray white spaces.Ralf Corsepius2004-04-151-1/+0
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* 2004-04-01 Ralf Corsepius <ralf_corsepius@rtems.org>Ralf Corsepius2004-04-011-1/+1
| | | | * cpu_asm.S: Include <rtems/asm.h> instead of <asm.h>.
* 2003-09-04 Joel Sherrill <joel@OARcorp.com>Joel Sherrill2003-09-041-1/+1
| | | | * cpu.c, cpu_asm.S: URL for license changed.
* 2001-11-14 Till Straumann <strauman@SLAC.Stanford.EDU>Joel Sherrill2001-11-141-98/+108
| | | | | | | * new_exception_processing/cpu_asm.S: Support double or single precision context switches. Note that doing a single precision context save/restore on a double precision PowerPC machine does not only result in rounding errors but also screws up the FPSCR register!
* 2001-10-12 Joel Sherrill <joel@OARcorp.com>Joel Sherrill2001-10-121-1/+0
| | | | | | | | | * mpc6xx/clock/c_clock.c, mpc6xx/clock/c_clock.h, mpc8xx/clock/clock.c, mpc8xx/timer/timer.c, new_exception_processing/cpu.c, new_exception_processing/cpu.h, new_exception_processing/cpu_asm.S, old_exception_processing/cpu.c, old_exception_processing/cpu.h, old_exception_processing/cpu_asm.S, old_exception_processing/rtems.S: Fixed typo.
* Merged of mcp750 and mvme2307 BSP by Eric Valette <valette@crf.canon.fr>.Joel Sherrill1999-12-021-0/+396
As part of this effort, the mpc750 libcpu code is now shared with the ppc6xx.
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