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| author | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2014-05-02 10:31:09 +0200 |
|---|---|---|
| committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2014-05-07 14:26:28 +0200 |
| commit | 38b59a6d3052654e356ae16b4a243c362312acce (patch) | |
| tree | 9d19ed78a331839a2f292572ddbfa44091efd347 /c/src/lib/libcpu/powerpc/new-exceptions/cpu_asm.S | |
| parent | score: Delete _SMP_Test_message_default_handler (diff) | |
| download | rtems-38b59a6d3052654e356ae16b4a243c362312acce.tar.bz2 | |
score: Implement forced thread migration
The current implementation of task migration in RTEMS has some
implications with respect to the interrupt latency. It is crucial to
preserve the system invariant that a task can execute on at most one
processor in the system at a time. This is accomplished with a boolean
indicator in the task context. The processor architecture specific
low-level task context switch code will mark that a task context is no
longer executing and waits that the heir context stopped execution
before it restores the heir context and resumes execution of the heir
task. So there is one point in time in which a processor is without a
task. This is essential to avoid cyclic dependencies in case multiple
tasks migrate at once. Otherwise some supervising entity is necessary to
prevent life-locks. Such a global supervisor would lead to scalability
problems so this approach is not used. Currently the thread dispatch is
performed with interrupts disabled. So in case the heir task is
currently executing on another processor then this prolongs the time of
disabled interrupts since one processor has to wait for another
processor to make progress.
It is difficult to avoid this issue with the interrupt latency since
interrupts normally store the context of the interrupted task on its
stack. In case a task is marked as not executing we must not use its
task stack to store such an interrupt context. We cannot use the heir
stack before it stopped execution on another processor. So if we enable
interrupts during this transition we have to provide an alternative task
independent stack for this time frame. This issue needs further
investigation.
Diffstat (limited to 'c/src/lib/libcpu/powerpc/new-exceptions/cpu_asm.S')
| -rw-r--r-- | c/src/lib/libcpu/powerpc/new-exceptions/cpu_asm.S | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/c/src/lib/libcpu/powerpc/new-exceptions/cpu_asm.S b/c/src/lib/libcpu/powerpc/new-exceptions/cpu_asm.S index dcd33df789..4e74996d4c 100644 --- a/c/src/lib/libcpu/powerpc/new-exceptions/cpu_asm.S +++ b/c/src/lib/libcpu/powerpc/new-exceptions/cpu_asm.S @@ -326,9 +326,29 @@ PROC (_CPU_Context_switch): stw r2, PPC_CONTEXT_OFFSET_GPR2(r3) +#ifdef RTEMS_SMP + /* Indicate that this context is no longer executing */ + msync + li r5, 0 + stb r5, PPC_CONTEXT_OFFSET_IS_EXECUTING(r3) +#endif + /* Restore context from r4 */ restore_context: +#ifdef RTEMS_SMP + /* Wait for context to stop execution if necessary */ +1: + lbz r5, PPC_CONTEXT_OFFSET_IS_EXECUTING(r4) + cmpwi r5, 0 + bne 1b + + /* Indicate that this context is executing */ + li r5, 1 + stb r5, PPC_CONTEXT_OFFSET_IS_EXECUTING(r4) + isync +#endif + #ifdef __ALTIVEC__ mr r14, r4 .extern _CPU_Context_switch_altivec |