| Commit message (Collapse) | Author | Age | Files | Lines |
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This patch is a part of the BSP source reorganization.
Update #3285.
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This patch is a part of the BSP source reorganization.
Update #3285.
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This patch is a part of the BSP source reorganization.
Update #3285.
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This patch is a part of the BSP source reorganization.
Update #3285.
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Cannot read or write MSR when executing in user mode. This
is used when RTEMS_PARAVIRT is defined.
Provide alternate methods to disable/enable interrupts
Closes #3306.
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A speciality of the RTEMS build system was the make preinstall step. It
copied header files from arbitrary locations into the build tree. The
header files were included via the -Bsome/build/tree/path GCC command
line option.
This has at least seven problems:
* The make preinstall step itself needs time and disk space.
* Errors in header files show up in the build tree copy. This makes it
hard for editors to open the right file to fix the error.
* There is no clear relationship between source and build tree header
files. This makes an audit of the build process difficult.
* The visibility of all header files in the build tree makes it
difficult to enforce API barriers. For example it is discouraged to
use BSP-specifics in the cpukit.
* An introduction of a new build system is difficult.
* Include paths specified by the -B option are system headers. This
may suppress warnings.
* The parallel build had sporadic failures on some hosts.
This patch removes the make preinstall step. All installed header
files are moved to dedicated include directories in the source tree.
Let @RTEMS_CPU@ be the target architecture, e.g. arm, powerpc, sparc,
etc. Let @RTEMS_BSP_FAMILIY@ be a BSP family base directory, e.g.
erc32, imx, qoriq, etc.
The new cpukit include directories are:
* cpukit/include
* cpukit/score/cpu/@RTEMS_CPU@/include
* cpukit/libnetworking
The new BSP include directories are:
* bsps/include
* bsps/@RTEMS_CPU@/include
* bsps/@RTEMS_CPU@/@RTEMS_BSP_FAMILIY@/include
There are build tree include directories for generated files.
The include directory order favours the most general header file, e.g.
it is not possible to override general header files via the include path
order.
The "bootstrap -p" option was removed. The new "bootstrap -H" option
should be used to regenerate the "headers.am" files.
Update #3254.
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Update #3254.
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For the SPE support we must store the upper half of r3 as well.
Update #3085.
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Use the saved MSR to account for FPU and AltiVec settings.
Update #2811.
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Update #3082.
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Implement thread dispatch code in ppc_exc_wrapup() similar to
ppc_exc_interrupt().
Update #2811.
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Fix link-time error on BSPs not using PPC_EXC_CONFIG_USE_FIXED_HANDLER.
Update #3085.
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Make PPC_EXC_CONFIG_USE_FIXED_HANDLER mandatory for BSPs using
ppc_exc_interrupt(). Pass exception number to bsp_interrupt_dispatch()
to allow processing of decrementer and doorbell exceptions as hypervisor
guest.
Update #3085.
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In 64-bit mode, the linker must have the ability to restore the TOC
pointer after an external function call.
Update #3082.
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Rename ppc_exc_wrap_async_normal_end to ppc_exc_interrupt_end to avoid a
bit of obfuscation.
Update #3082.
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Update #3082.
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Update #3082.
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Use a specific define for the interrupt exception frame size.
Update #3082.
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Rename ppc_exc_wrap_async_normal to ppc_exc_interrupt to avoid a bit of
obfuscation.
Update #3082.
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Avoid use of small-data area, since it is not supported in the ELFv2 ABI
by GCC.
Update #3082.
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There is no need to save the thread pointer in _CPU_Context_switch()
since it is a thread invariant. It is initialized once in
_CPU_Context_Initialize().
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Closes #3015.
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Use r8 instead of r5 to slightly optimize _CPU_Context_switch(). It is
not a big deal, however, we already assume r12 is used by
_CPU_Context_switch(). Treat r5 the in same way.
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Update #2751.
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Update #2751.
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Callers of _Thread_Do_dispatch() must have a valid
Per_CPU_Control::Stats::thread_dispatch_disabled_instant.
Call _Profiling_Outer_most_interrupt_entry_and_exit() with the interrupt
stack to not exceed Per_CPU_Control::Interrupt_frame.
Update #2751.
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Update #2751.
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Use a processor-specific interrupt frame during context switches in case
the executing thread is longer executes on the processor and the heir
thread is about to start execution. During this period we must not use
a thread stack for interrupt processing.
Update #2809.
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Rename ppc_exc_min_frame to CPU_Interrupt_frame. Move it and the
corresponding defines to <rtems/score/cpuimpl.h>.
Update #2809.
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We need the unmodified r4 for get_potential_new_heir.
This partially reverts commit 8d785f72d9610fb80a65d7848404f0f7507e026c.
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Properly pass the stack aligned context to _CPU_Context_switch_altivec()
since _CPU_altivec_ctxt_off defined via ppc_context.
Close #2761.
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According to the C11 and C++11 memory models only a read-modify-write
operation guarantees that we read the last value written in modification
order. Avoid the sequential consistent thread fence and instead use the
inter-processor interrupt to set the thread dispatch necessary
indicator.
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Store the floating-point unit property in the thread control block
regardless of the CPU_HARDWARE_FP and CPU_SOFTWARE_FP settings. Make
sure the floating-point unit is only enabled for the corresponding
multilibs. This helps targets which have a volatile only floating point
context like SPARC for example.
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Add AltiVec and FPU support to the Context_Control in case we use the
e6500 multilib.
Add PPC_MULTILIB_ALTIVEC and PPC_MULTILIB_FPU multilib defines. Add
non-volatile AltiVec and FPU context to Context_Control. Add save/restore of
non-volatile AltiVec and FPU to _CPU_Context_switch(). Add save/restore
of volatile AltiVec and FPU context to the exception code. Adjust data
cache optimizations for the new context and cache line size.
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This is not correct, but works for now.
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Provide floating point context support only if PPC_HAS_FPU == 1.
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