diff options
| author | Joel Sherrill <joel@rtems.org> | 2018-03-12 14:53:09 -0500 |
|---|---|---|
| committer | Joel Sherrill <joel@rtems.org> | 2018-03-13 09:55:23 -0500 |
| commit | 0a7a30d19d7d2e3067fc7d7be0d54730b8275f2f (patch) | |
| tree | bdb81bd29cb7ad96d43897ac126eae39e49a45a2 /c/src/lib/libcpu/powerpc/new-exceptions/cpu_asm.S | |
| parent | Add ARM Paravirtualization support (diff) | |
| download | rtems-0a7a30d19d7d2e3067fc7d7be0d54730b8275f2f.tar.bz2 | |
Add PowerPC paravirtualization support
Cannot read or write MSR when executing in user mode. This
is used when RTEMS_PARAVIRT is defined.
Provide alternate methods to disable/enable interrupts
Closes #3306.
Diffstat (limited to 'c/src/lib/libcpu/powerpc/new-exceptions/cpu_asm.S')
| -rw-r--r-- | c/src/lib/libcpu/powerpc/new-exceptions/cpu_asm.S | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/c/src/lib/libcpu/powerpc/new-exceptions/cpu_asm.S b/c/src/lib/libcpu/powerpc/new-exceptions/cpu_asm.S index cdbf403dce..5b095d9cea 100644 --- a/c/src/lib/libcpu/powerpc/new-exceptions/cpu_asm.S +++ b/c/src/lib/libcpu/powerpc/new-exceptions/cpu_asm.S @@ -128,12 +128,15 @@ PROC (_CPU_Context_save_fp): /* A FP context switch may occur in an ISR or exception handler when the FPU is not * available. Therefore, we must explicitely enable it here! */ +#if !defined(PPC_DISABLE_MSR_ACCESS) mfmsr r4 andi. r5,r4,MSR_FP bne 1f ori r5,r4,MSR_FP mtmsr r5 isync +#endif /* END PPC_DISABLE_MSR_ACCESS */ + 1: lwz r3, 0(r3) STF f0, FP_0(r3) @@ -170,9 +173,12 @@ PROC (_CPU_Context_save_fp): STF f31, FP_31(r3) mffs f2 STF f2, FP_FPSCR(r3) +#if !defined(PPC_DISABLE_MSR_ACCESS) bne 1f mtmsr r4 isync +#endif /* END PPC_DISABLE_MSR_ACCESS */ + 1: blr @@ -196,12 +202,15 @@ PROC (_CPU_Context_restore_fp): /* A FP context switch may occur in an ISR or exception handler when the FPU is not * available. Therefore, we must explicitely enable it here! */ +#if !defined(PPC_DISABLE_MSR_ACCESS) mfmsr r4 andi. r5,r4,MSR_FP bne 1f ori r5,r4,MSR_FP mtmsr r5 isync +#endif /* END PPC_DISABLE_MSR_ACCESS */ + 1: LDF f2, FP_FPSCR(r3) mtfsf 255, f2 @@ -238,8 +247,11 @@ PROC (_CPU_Context_restore_fp): LDF f30, FP_30(r3) LDF f31, FP_31(r3) bne 1f +#if !defined(PPC_DISABLE_MSR_ACCESS) mtmsr r4 isync +#endif /* END PPC_DISABLE_MSR_ACCESS */ + 1: blr #endif /* PPC_HAS_FPU == 1 */ @@ -266,7 +278,9 @@ PROC (_CPU_Context_switch): /* Save context to r3 */ GET_SELF_CPU_CONTROL r12 +#if !defined(PPC_DISABLE_MSR_ACCESS) mfmsr r6 +#endif /* END PPC_DISABLE_MSR_ACCESS */ mfcr r7 mflr r8 lwz r11, PER_CPU_ISR_DISPATCH_DISABLE(r12) @@ -529,7 +543,9 @@ restore_context: mtlr r8 mtcr r7 +#if !defined(PPC_DISABLE_MSR_ACCESS) mtmsr r6 +#endif /* END PPC_DISABLE_MSR_ACCESS */ stw r11, PER_CPU_ISR_DISPATCH_DISABLE(r12) #ifdef BSP_USE_SYNC_IN_CONTEXT_SWITCH |