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* bsps/powerpc: Move basic support to bspsSebastian Huber2018-03-191-138/+0
| | | | | | This patch is a part of the BSP source reorganization. Update #3285.
* Add PowerPC paravirtualization supportJoel Sherrill2018-03-131-3/+7
| | | | | | | | | Cannot read or write MSR when executing in user mode. This is used when RTEMS_PARAVIRT is defined. Provide alternate methods to disable/enable interrupts Closes #3306.
* powerpc: Add 64-bit context/interrupt supportSebastian Huber2017-08-221-5/+1
| | | | Update #3082.
* powerpc: 64-bit _CPU_Context_Initialize() supportSebastian Huber2017-08-221-7/+9
| | | | Update #3082.
* score: Fix ARM and PowerPC context initializationSebastian Huber2016-12-021-0/+1
| | | | Update #2751.
* score: Add Thread_Control::is_fpSebastian Huber2015-06-091-17/+1
| | | | | | | | Store the floating-point unit property in the thread control block regardless of the CPU_HARDWARE_FP and CPU_SOFTWARE_FP settings. Make sure the floating-point unit is only enabled for the corresponding multilibs. This helps targets which have a volatile only floating point context like SPARC for example.
* powerpc: AltiVec and FPU context supportSebastian Huber2015-01-131-3/+14
| | | | | | | | | | | Add AltiVec and FPU support to the Context_Control in case we use the e6500 multilib. Add PPC_MULTILIB_ALTIVEC and PPC_MULTILIB_FPU multilib defines. Add non-volatile AltiVec and FPU context to Context_Control. Add save/restore of non-volatile AltiVec and FPU to _CPU_Context_switch(). Add save/restore of volatile AltiVec and FPU context to the exception code. Adjust data cache optimizations for the new context and cache line size.
* Eliminate use of /*PAGE and clean up formattingJoel Sherrill2014-10-091-9/+5
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* score: Fix CPU context usage on SMPSebastian Huber2014-05-081-6/+0
| | | | | | | | | | We must not alter the is executing indicator in _CPU_Context_Initialize() since this would cause an invalid state during a self restart. The is executing indicator must be valid at creation time since otherwise _Thread_Kill_zombies() uses an undefined value for not started threads. This could result in a system life lock.
* score: Implement forced thread migrationSebastian Huber2014-05-071-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current implementation of task migration in RTEMS has some implications with respect to the interrupt latency. It is crucial to preserve the system invariant that a task can execute on at most one processor in the system at a time. This is accomplished with a boolean indicator in the task context. The processor architecture specific low-level task context switch code will mark that a task context is no longer executing and waits that the heir context stopped execution before it restores the heir context and resumes execution of the heir task. So there is one point in time in which a processor is without a task. This is essential to avoid cyclic dependencies in case multiple tasks migrate at once. Otherwise some supervising entity is necessary to prevent life-locks. Such a global supervisor would lead to scalability problems so this approach is not used. Currently the thread dispatch is performed with interrupts disabled. So in case the heir task is currently executing on another processor then this prolongs the time of disabled interrupts since one processor has to wait for another processor to make progress. It is difficult to avoid this issue with the interrupt latency since interrupts normally store the context of the interrupted task on its stack. In case a task is marked as not executing we must not use its task stack to store such an interrupt context. We cannot use the heir stack before it stopped execution on another processor. So if we enable interrupts during this transition we have to provide an alternative task independent stack for this time frame. This issue needs further investigation.
* score: Clarify TLS supportSebastian Huber2014-04-171-1/+1
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* Change all references of rtems.com to rtems.org.Chris Johns2014-03-211-1/+1
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* Add thread-local storage (TLS) supportSebastian Huber2014-02-041-3/+13
| | | | | Tested and implemented on ARM, m68k, PowerPC and SPARC. Other architectures need more work.
* powerpc: Add r2 to CPU contextSebastian Huber2013-11-181-0/+2
| | | | The r2 may be used for thread-local storage.
* powerpc: Fix Altivec supportSebastian Huber2013-06-261-1/+1
| | | | Use the right context.
* score: Add INTERNAL_ERROR_CPU_ISR_INSTALL_VECTORSebastian Huber2012-11-151-22/+0
| | | | | Use INTERNAL_ERROR_CPU_ISR_INSTALL_VECTOR on PowerPC for _CPU_ISR_install_vector().
* powerpc: Delete _CPU_Install_interrupt_stack()Sebastian Huber2012-11-141-9/+0
| | | | This function is only used if CPU_HAS_HARDWARE_INTERRUPT_STACK == TRUE.
* powerpc: Simplify context switchSebastian Huber2012-06-041-29/+5
| | | | | | | | | | | | | | | | | | | PowerPC cores with the SPE (Signal Processing Extension) have 64-bit general-purpose registers. The SPE context switch code has been merged with the standard context switch code. The context switch may use cache operations to increase the performance. It will be ensured that the context is 32-byte aligned (PPC_DEFAULT_CACHE_LINE_SIZE). This increases the overall memory size of the context area in the thread control block slightly. The general-purpose registers GPR2 and GPR13 are no longer part of the context. The BSP must initialize these registers during startup (usually initialized by the __eabi() function). The new BSP option BSP_USE_DATA_CACHE_BLOCK_TOUCH can be used to enable the dcbt instruction in the context switch. The new BSP option BSP_USE_SYNC_IN_CONTEXT_SWITCH can be used to enable sync and isync instructions in the context switch. This should be not necessary in most cases.
* Remove All CVS Id Strings Possible Using a ScriptJoel Sherrill2012-05-111-2/+0
| | | | | | | | | | | | Script does what is expected and tries to do it as smartly as possible. + remove occurrences of two blank comment lines next to each other after Id string line removed. + remove entire comment blocks which only exited to contain CVS Ids + If the processing left a blank line at the top of a file, it was removed.
* 2011-07-21 Sebastian Huber <sebastian.huber@embedded-brains.de>Sebastian Huber2011-07-211-6/+11
| | | | | | | | | | | | PR 1799/bsps * new-exceptions/bspsupport/ppc_exc_async_normal.S: New file. * new-exceptions/cpu.c, new-exceptions/cpu_asm.S, new-exceptions/bspsupport/ppc_exc_asm_macros.h, new-exceptions/bspsupport/ppc_exc_global_handler.c, new-exceptions/bspsupport/ppc_exc_prologue.c, new-exceptions/bspsupport/vectors.h: Added support for SPE. * configure.ac, preinstall.am, Makefile.am: Added support for qoriq BSPs.
* 2011-02-11 Ralf Corsépius <ralf.corsepius@rtems.org>Ralf Corsepius2011-02-111-2/+2
| | | | | | | | | | | | | | * e500/mmu/mmu.c, mpc505/ictrl/ictrl.c, mpc505/timer/timer.c, mpc5xx/ictrl/ictrl.c, mpc5xx/timer/timer.c, mpc6xx/altivec/vec_sup.c, mpc6xx/clock/c_clock.c, mpc6xx/mmu/bat.c, mpc6xx/mmu/bat.h, mpc6xx/mmu/pte121.c, mpc8260/timer/timer.c, mpc8xx/timer/timer.c, new-exceptions/cpu.c, new-exceptions/bspsupport/ppc_exc_initialize.c, ppc403/clock/clock.c, ppc403/console/console.c, ppc403/console/console.c.polled, ppc403/console/console405.c, ppc403/irq/ictrl.c, ppc403/tty_drv/tty_drv.c, rtems/powerpc/cache.h, shared/include/powerpc-utility.h, shared/src/cache.c: Use "__asm__" instead of "asm" for improved c99-compliance.
* 2009-12-01 Till Straumann <strauman@slac.stanford.edu>Till Straumann2009-12-021-0/+8
| | | | | | | | | * new-exceptions/cpu.c, new-exceptions/cpu_asm.S, new-exceptions/bspsupport/ppc_exc_asm_macros.h, new-exceptions/bspsupport/ppc_exc_initialize.c, new-exceptions/bspsupport/vectors.h: Added AltiVec support (save/restore volatile vregs across exceptions).
* Whitespace removal.Ralf Corsepius2009-11-301-3/+3
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* 2009-02-13 Joel Sherrill <joel.sherrill@OARcorp.com>Joel Sherrill2009-02-131-6/+2
| | | | * new-exceptions/cpu.c: Correct prototype of _CPU_Initialize.
* Convert to "bool".Ralf Corsepius2008-09-061-1/+1
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* 2008-07-16 Till Straumann <strauman@slac.stanford.edu>Till Straumann2008-07-161-2/+8
| | | | | * new-exceptions/cpu.c: propagate R2 to all task contexts even if the ABI is SVR4. Cannot hurt...
* 2008-07-16 Till Straumann <strauman@slac.stanford.edu>Till Straumann2008-07-161-2/+16
| | | | | * new-exceptions/cpu.c: use ppc_interrupt_get_disable_mask() to determine which bits to set/clear from _CPU_Context_Initialize().
* adapted powerpc exception codeThomas Doerfler2008-07-111-9/+1
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* 2007-12-04 Joel Sherrill <joel.sherrill@OARcorp.com>Joel Sherrill2007-12-041-10/+8
| | | | | | | * mpc5xx/console-generic/console-generic.c, mpc8260/timer/timer.c, new-exceptions/cpu.c, old-exceptions/cpu.c: Move interrupt_stack_size field from CPU Table to Configuration Table. Eliminate CPU Table from all ports. Delete references to CPU Table in all forms.
* Never allow the FPU to be switched on for integer-only tasksTill Straumann2006-06-191-10/+10
| | | | (new gcc may use FP regs implicitely).
* 2005-02-17 Ralf Corsepius <ralf.corsepius@rtems.org>Ralf Corsepius2005-02-171-4/+1
| | | | | | | * new-exceptions/cpu.c, rtems/powerpc/powerpc.h: Remove CPU_MINIMUM_STACK_FRAME_SIZE. Use PPC_MINIMUM_STACK_FRAME_SIZE instead. * rtems/powerpc/powerpc.h: Add PPC_MINIMUM_STACK_FRAME_SIZE.
* 2005-02-15 Ralf Corsepius <ralf.corsepius@rtems.org>Ralf Corsepius2005-02-161-0/+3
| | | | * new-exceptions/cpu.c: Add CPU_MINIMUM_STACK_FRAME_SIZE.
* 2005-02-15 Ralf Corsepius <ralf.corsepius@rtems.org>Ralf Corsepius2005-02-151-0/+22
| | | | * new-exceptions/cpu.c (_CPU_ISR_install_vector): New.
* 2005-02-14 Ralf Corsepius <ralf.corsepius@rtems.org>Ralf Corsepius2005-02-141-0/+1
| | | | * cpu.c, cpu_asm.S, irq_stub.S: #include <rtems/powerpc/powerpc.h>.
* Remove duplicate white lines.Ralf Corsepius2004-04-211-3/+0
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* Remove stray white spaces.Ralf Corsepius2004-04-211-4/+4
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* Remove stray white spaces.Ralf Corsepius2004-04-151-1/+0
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* 2004-03-31 Ralf Corsepius <ralf_corsepius@rtems.org>Ralf Corsepius2004-03-311-9/+9
| | | | * cpu.c: Convert to using c99 fixed size types.
* 2003-09-04 Joel Sherrill <joel@OARcorp.com>Joel Sherrill2003-09-041-1/+1
| | | | * cpu.c, cpu_asm.S: URL for license changed.
* 2003-07-18 Till Straumann <strauman@slac.stanford.edu>Joel Sherrill2003-07-231-24/+8
| | | | | | PR 288/rtems * support/new_exception_processing/cpu.c: _ISR_Nest_level is now properly maintained and does not reside in SPRG0.
* 2003-03-18 Till Straumann <strauman@slac.stanford.edu>Joel Sherrill2003-03-181-0/+21
| | | | | PR 356/bsps * cpu.c: This patch makes RTEMS/PowerPC eabi compliant.
* 2002-11-01 Joel Sherrill <joel@OARcorp.com>Joel Sherrill2002-11-011-0/+8
| | | | | | * cpu.c: Currently only the mpc8260 BSP supports interrupt nesting. NOTE: These needs to be generalized as the patch is applied to other BSPs.
* 2001-05-14 Till Straumann <strauman@slac.stanford.edu>Joel Sherrill2002-05-141-1/+13
| | | | | | | | | | | | | | | | | | | | | * cpu.c: Per PR211 fix saving/restoring floating point context. The fpsave and fprestore routines are only used in a executing context which _is_ fp and hence has the FPU enabled. The current behavior required the FPU always to be on which is very dangerous if lazy context switching is used. [Joel Note: Some ports explicitly enabled the FPU in the FP save and restore routines to avoid this.] The patch also makes sure (on powerpc only) that the FPU is disabled for integer tasks. Note that this is crucial if deferred fp context switching is used. Otherwise, fp context corruption may go undetected! Also note that even tasks which merely push/pop FP registers to/from the stack without modifying them still MUST be FP tasks - otherwise (if lazy FP context switching is used), FP register corruption (of other, FP, tasks may occur)! Furthermore, (on PPC) by default, lazy FP context save/restore is _disabled_.
* 2001-11-28 Joel Sherrill <joel@OARcorp.com>,Joel Sherrill2001-11-281-1/+14
| | | | | | | | | | This was tracked as PR91. * rtems/score/cpu.h: Added CPU_PROVIDES_ISR_IS_IN_PROGRESS macro which is used to specify if the port uses the standard macro for this (FALSE). A TRUE setting indicates the port provides its own implementation. * rtems/score/c_isr.inl: Deleted and contents merged into cpu.c. * cpu.c: Received contents of c_isr.inl. * Makefile.am: Deleted reference to c_isr.inl.
* 2001-10-12 Joel Sherrill <joel@OARcorp.com>Joel Sherrill2001-10-121-1/+0
| | | | | | | | | * mpc6xx/clock/c_clock.c, mpc6xx/clock/c_clock.h, mpc8xx/clock/clock.c, mpc8xx/timer/timer.c, new_exception_processing/cpu.c, new_exception_processing/cpu.h, new_exception_processing/cpu_asm.S, old_exception_processing/cpu.c, old_exception_processing/cpu.h, old_exception_processing/cpu_asm.S, old_exception_processing/rtems.S: Fixed typo.
* Merged of mcp750 and mvme2307 BSP by Eric Valette <valette@crf.canon.fr>.Joel Sherrill1999-12-021-0/+116
As part of this effort, the mpc750 libcpu code is now shared with the ppc6xx.
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