diff options
author | Joel Sherrill <joel@rtems.org> | 2018-03-12 14:53:09 -0500 |
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committer | Joel Sherrill <joel@rtems.org> | 2018-03-13 09:55:23 -0500 |
commit | 0a7a30d19d7d2e3067fc7d7be0d54730b8275f2f (patch) | |
tree | bdb81bd29cb7ad96d43897ac126eae39e49a45a2 /c/src/lib/libcpu/powerpc/new-exceptions/cpu.c | |
parent | Add ARM Paravirtualization support (diff) | |
download | rtems-0a7a30d19d7d2e3067fc7d7be0d54730b8275f2f.tar.bz2 |
Add PowerPC paravirtualization support
Cannot read or write MSR when executing in user mode. This
is used when RTEMS_PARAVIRT is defined.
Provide alternate methods to disable/enable interrupts
Closes #3306.
Diffstat (limited to 'c/src/lib/libcpu/powerpc/new-exceptions/cpu.c')
-rw-r--r-- | c/src/lib/libcpu/powerpc/new-exceptions/cpu.c | 10 |
1 files changed, 7 insertions, 3 deletions
diff --git a/c/src/lib/libcpu/powerpc/new-exceptions/cpu.c b/c/src/lib/libcpu/powerpc/new-exceptions/cpu.c index ae5065daa4..7c37f0e0d8 100644 --- a/c/src/lib/libcpu/powerpc/new-exceptions/cpu.c +++ b/c/src/lib/libcpu/powerpc/new-exceptions/cpu.c @@ -64,7 +64,7 @@ void _CPU_Context_Initialize( ) { ppc_context *the_ppc_context; - uint32_t msr_value; + uint32_t msr_value = 0; uintptr_t sp; uintptr_t stack_alignment; @@ -75,10 +75,11 @@ void _CPU_Context_Initialize( sp = (uintptr_t) memset((void *) sp, 0, PPC_MINIMUM_STACK_FRAME_SIZE); - _CPU_MSR_GET( msr_value ); - the_ppc_context = ppc_get_context( the_context ); +#if !defined(PPC_DISABLE_MSR_ACCESS) + _CPU_MSR_GET( msr_value ); + /* * Setting the interrupt mask here is not strictly necessary * since the IRQ level will be established from _Thread_Handler() @@ -113,7 +114,10 @@ void _CPU_Context_Initialize( #ifdef PPC_MULTILIB_ALTIVEC msr_value |= MSR_VE; +#endif +#endif /* END PPC_DISABLE_MSR_ACCESS */ +#ifdef PPC_MULTILIB_ALTIVEC the_ppc_context->vrsave = 0; #endif |