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* bsps/riscv: add riscv/kendrytek210 BSP variant source changesAlan Cudmore2023-03-281-0/+4
| | | | | | | | | This patch adds support for the Kendryte K210 RISC-V BSP variant. The SoC uses the existing Interrupt Controller, Timer, and console UART. It only needs SoC specific initialization and an embedded device tree binary similar to the polarfire SoC BSP. Updates #4876
* bsp/riscv: Add NOEL-V BSPMartin Aberg2022-09-061-0/+2
| | | | | | | | | | | | | | | | | | | | Added support for Cobham Gaisler NOEL-V systems. The NOEL-V support is implemented as a riscv BSP. Both 32-bit and 64-bit processor systems are supported. Cobham Gaisler's NOEL-V RISC-V processor IP is described here: https://www.gaisler.com/NOELV Compatible with the following NOEL-V FPGA example design ranges available from Cobham Gaisler. Follow the links for free bit-streams, DTS/DTB, user's manuals and quick-start guides: - NOEL-ARTYA7-EX (https://www.gaisler.com/NOEL-ARTYA7) - NOEL-PF-EX (https://www.gaisler.com/NOEL-PF) - NOEL-XCKU-EX (https://www.gaisler.com/NOEL-XCKU) Uses the shared GRLIB APBUART console driver "apbuart_termios.c". APBUART devices are probed using device tree. Closes #4225.
* bsps: Adjust bsp.h Doxygen groupsSebastian Huber2019-03-081-0/+20
| | | | Update #3706.
* bsp/riscv: Add PLIC supportSebastian Huber2018-07-251-0/+2
| | | | Update #3433.
* bsp/riscv: Rework clock driverSebastian Huber2018-06-281-22/+0
| | | | | | | Use device tree provided timebase frequency. Do not write to read-only mtime register. Update #3433.
* bsp/riscv: Add device tree supportSebastian Huber2018-06-281-0/+2
| | | | Update #3433.
* bsp/riscv_generic: Rename to "riscv"Sebastian Huber2018-06-271-0/+73
Update #3433.
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