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* bsps/riscv: add riscv/kendrytek210 BSP variant source changesAlan Cudmore2023-03-281-1/+1
| | | | | | | | | This patch adds support for the Kendryte K210 RISC-V BSP variant. The SoC uses the existing Interrupt Controller, Timer, and console UART. It only needs SoC specific initialization and an embedded device tree binary similar to the polarfire SoC BSP. Updates #4876
* bsps/riscv/riscv: Fix fe310_uart_readAlan Cudmore2022-09-191-2/+5
| | | | | | | | | | | Note: Resending after learning how to use git send-email, please disregard previous message. This fixes the riscv fe310 console driver fe310_uart_read function. The function reads the RX status/data register to check if data is available, but discards the data and reads it a seconds time. Also cleared the interrupt enable bit in the first_open function. Close #4719
* bsp/riscv: Fix format and warningsSebastian Huber2019-11-141-33/+17
| | | | Update #3785.
* riscv: add freedom E310 Arty A7 bspPragnesh Patel2019-10-231-0/+118
Added support for Sifive Freedom FE310 soc on Arty A7 FPGA board. Update #3785. Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
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