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| author | Alan Cudmore <alan.cudmore@gmail.com> | 2023-03-15 09:41:53 -0400 |
|---|---|---|
| committer | Joel Sherrill <joel@rtems.org> | 2023-03-28 14:04:04 -0500 |
| commit | 26853a06243857015d47abc9e2c2216f5bf7ab7c (patch) | |
| tree | af2e250dd87babb7dd42b19592d18a8c8a4a0daf /bsps/riscv/riscv/console/fe310-uart.c | |
| parent | bsps/riscv: add device tree source and device tree blob header for k210 bsp v... (diff) | |
| download | rtems-26853a06243857015d47abc9e2c2216f5bf7ab7c.tar.bz2 | |
bsps/riscv: add riscv/kendrytek210 BSP variant source changes
This patch adds support for the Kendryte K210 RISC-V BSP variant.
The SoC uses the existing Interrupt Controller, Timer, and console UART.
It only needs SoC specific initialization and an embedded device tree binary
similar to the polarfire SoC BSP.
Updates #4876
Diffstat (limited to 'bsps/riscv/riscv/console/fe310-uart.c')
| -rw-r--r-- | bsps/riscv/riscv/console/fe310-uart.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/bsps/riscv/riscv/console/fe310-uart.c b/bsps/riscv/riscv/console/fe310-uart.c index 506521add0..ddabcff4c8 100644 --- a/bsps/riscv/riscv/console/fe310-uart.c +++ b/bsps/riscv/riscv/console/fe310-uart.c @@ -53,7 +53,7 @@ static void fe310_uart_write ( fe310_uart_context * ctx = (fe310_uart_context*) base; size_t i; - ctx->regs->div = riscv_get_core_frequency() / 115200 - 1; + ctx->regs->div = (riscv_get_core_frequency() / 115200 - 1) & 0xFFFF; ctx->regs->txctrl |= 1; ctx->regs->rxctrl |= 1; |