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* dev/irq: Improve Doxgyen group assignmentsSebastian Huber2024-04-165-17/+51
| | | | | Make the GIC interrupt controller support a subgroup of the generic interrupt controller support.
* bsps: Move declarations to <bsp/irq-generic.h>Sebastian Huber2024-03-271-11/+0
| | | | | | | | | | | Move declarations of bsp_interrupt_get_affinity() and bsp_interrupt_set_affinity() to <bsp/irq-generic.h>. Canonicalize the <bsp/irq.h> includes. Implement bsp_interrupt_get_affinity() and bsp_interrupt_set_affinity() only if needed (usually RTEMS_SMP). Provide stub implementations for i386 to fix build errors.
* dev/irq: Optional arm_gic_irq_processor_count()Sebastian Huber2024-03-201-0/+2
| | | | Provide arm_gic_irq_processor_count() only in SMP configurations.
* tm27: Add optional TM27_INTERRUPT_VECTOR_DEFAULTSebastian Huber2023-12-191-0/+2
| | | | | | | Let the BSP define TM27_INTERRUPT_VECTOR_DEFAULT to more efficiently and reliably get the TM27 default interrupt vector. Update #3716.
* bsps/arm: Use interrupt entry for <tm27.h>Sebastian Huber2023-05-261-18/+34
| | | | | Avoid a dynamic memory allocation for the <tm27.h> interrupts. Replace assert() with _Assert().
* Update company nameSebastian Huber2023-05-205-5/+5
| | | | | The embedded brains GmbH & Co. KG is the legal successor of embedded brains GmbH.
* tm27: Avoid function pointer castsSebastian Huber2023-01-241-2/+2
| | | | | | | Add TM27_USE_VECTOR_HANDLER to select the interrupt handler type used by the <tm27.h> implementation. Close #4820.
* irq/arm-gicv3.h: Customize CPU Interface initSebastian Huber2022-07-121-21/+37
| | | | | | | Use the existing WRITE_SR() abstraction to access the interrupt group 0 and 1 enable registers. This fixes the build for the AArch32 target. Add BSP options which define the initial values of CPU Interface registers.
* bsps/include: Change license to BSD-2Joel Sherrill2022-07-114-12/+88
| | | | Updates #3053.
* aarch64/gicv3: Remove accesses to secure registersChris Johns2022-06-161-3/+15
| | | | | | RTEMS runs at EL1 and the removed register accesses are for EL3 or the TF-A. This change aligns our driver with the Linux and FreeBSD ones.
* bsps: Add gicv3_get_attributes()Sebastian Huber2022-04-061-0/+32
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* bsps: Add gicv3_sgi_ppi_get_priority()Sebastian Huber2022-04-061-0/+10
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* bsps: Add gicv3_sgi_ppi_set_priority()Sebastian Huber2022-04-061-0/+11
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* bsps: Move gicv3_init_cpu_interface()Sebastian Huber2022-04-061-0/+27
| | | | Make the processor index a parameter.
* bsps: Move gicv3_init_dist()Sebastian Huber2022-04-061-0/+37
| | | | Make the distributor register block a parameter.
* bsps: Add gicv3_sgi_ppi_disable()Sebastian Huber2022-04-061-0/+10
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* bsps: Add gicv3_sgi_ppi_enable()Sebastian Huber2022-04-061-0/+15
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* bsps: Add gicv3_sgi_ppi_is_enabled()Sebastian Huber2022-04-061-0/+10
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* bsps: Add gicv3_ppi_clear_pending()Sebastian Huber2022-04-061-0/+10
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* bsps: Add gicv3_ppi_set_pending()Sebastian Huber2022-04-061-0/+10
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* bsps: Add gicv3_trigger_sgi()Sebastian Huber2022-04-061-0/+21
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* bsps: Add gicv3_sgi_ppi_is_pending()Sebastian Huber2022-04-061-0/+11
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* bsps: Add <dev/irq/arm-gicv3.h>Sebastian Huber2022-04-061-0/+162
| | | | | | | | Separate the Interrupt Manager implementation from the generic Arm GICv3 support. Move parts of the Arm GICv3 support into a new header file. This helps to support systems with a clustered structure in which multiple GICv3 instances are present. For example, two clusters of two Cortex-R52 cores where each cluster has a dedicated GICv3 instance.
* bsps/include/: Scripted embedded brains header file clean upJoel Sherrill2022-03-104-24/+0
| | | | Updates #4625.
* bsps/irq: Implement new directives for GICv2/3Sebastian Huber2021-07-261-0/+3
| | | | Update #3269.
* bsps/irq: bsp_interrupt_set_affinity()Sebastian Huber2021-07-261-1/+1
| | | | | | Return a status code for bsp_interrupt_set_affinity(). Update #3269.
* bsps/irq: bsp_interrupt_get_affinity()Sebastian Huber2021-07-261-1/+1
| | | | | | Return a status code for bsp_interrupt_get_affinity(). Update #3269.
* bsps/dev/irq: make icspicfgr an indexable arrayGedare Bloom2021-06-241-4/+2
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* bsps: Allow override of ARM TM27 IRQsKinsey Moore2021-03-051-0/+4
| | | | | | ZynqMP hardware appears to have an odd hard-wired SGI implementation in which the SGIs are permanently set as enabled or disabled. Allow the TM27 IRQs to be overridden as necessary.
* bsps: Use header file for GIC architecture supportSebastian Huber2020-12-231-13/+0
| | | | | | This avoids a function call overhead in the interrupt dispatching. Update #4202.
* bsps: Remove gicvx_interrupt_dispatch()Sebastian Huber2020-12-161-6/+0
| | | | | | Avoid one level of indirection. Update #4202.
* bsps: Add GICv3 arm_gic_irq_processor_count()Sebastian Huber2020-12-161-6/+1
| | | | Update #4202.
* tm27: Use generic cpu index accessorKinsey Moore2020-12-111-3/+2
| | | | | | The arm_cp15 function for accessing the current CPU index is specific to ARMv7 while this header is used for ARMv8 as well. Instead, use a generic accessor that is part of the standard CPU API.
* bsps: Remove ARM GIC SGI target filterSebastian Huber2020-12-102-15/+2
| | | | | | | Remove the target filter for software-generated interrupts since this feature is not supported by the affinity routing in GICv3. Update #4202.
* bsps: Fix GICv3 arm_gic_trigger_sgi()Sebastian Huber2020-12-102-6/+7
| | | | | | | | Use the targets parameter to determine the targets of the SGI. Change targets parameter type to 32-bit to ease the parameter passing. GICv3 supports up to 16 targets. Update #4202.
* bsps: Move ARM GICv2 driver to bsps/sharedKinsey Moore2020-12-021-2/+2
| | | | | This moves the ARM GICv2 driver to bsps/shared to be usable by AArch64 code.
* bsps: Break out AArch32 GICv3 supportKinsey Moore2020-10-054-0/+705
This breaks out AArch32-specific code so that the shared GICv3 code can be reused by other architectures.
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