bsps: Fix GICv3 arm_gic_trigger_sgi()

Use the targets parameter to determine the targets of the SGI.  Change
targets parameter type to 32-bit to ease the parameter passing.  GICv3
supports up to 16 targets.

Update #4202.

2 files changed, 7 insertions, 6 deletions

diff --git a/bsps/include/dev/irq/arm-gic-irq.h b/bsps/include/dev/irq/arm-gic-irq.h
index d63fce32d1..ae0a68f7bb 100644
--- a/bsps/include/dev/irq/arm-gic-irq.h
+++ b/bsps/include/dev/irq/arm-gic-irq.h
@@ -88,13 +88,13 @@ typedef enum {
 void arm_gic_trigger_sgi(
   rtems_vector_number vector,
   arm_gic_irq_software_irq_target_filter filter,
-  uint8_t targets
+  uint32_t targets
 );
 
 static inline rtems_status_code arm_gic_irq_generate_software_irq(
   rtems_vector_number vector,
   arm_gic_irq_software_irq_target_filter filter,
-  uint8_t targets
+  uint32_t targets
 )
 {
   rtems_status_code sc = RTEMS_SUCCESSFUL;
diff --git a/bsps/include/dev/irq/arm-gic-tm27.h b/bsps/include/dev/irq/arm-gic-tm27.h
index 95f3077716..bfec3b22e0 100644
--- a/bsps/include/dev/irq/arm-gic-tm27.h
+++ b/bsps/include/dev/irq/arm-gic-tm27.h
@@ -31,6 +31,7 @@
 
 #include <bsp.h>
 #include <bsp/irq.h>
+#include <libcpu/arm-cp15.h>
 
 #define MUST_WAIT_FOR_INTERRUPT 1
 
@@ -79,8 +80,8 @@ static inline void Cause_tm27_intr(void)
 {
   rtems_status_code sc = arm_gic_irq_generate_software_irq(
     ARM_GIC_TM27_IRQ_LOW,
-    ARM_GIC_IRQ_SOFTWARE_IRQ_TO_SELF,
-    0
+    ARM_GIC_IRQ_SOFTWARE_IRQ_TO_ALL_IN_LIST,
+    1U << (arm_cp15_get_multiprocessor_affinity() & 0xff)
   );
   assert(sc == RTEMS_SUCCESSFUL);
 }
@@ -94,8 +95,8 @@ static inline void Lower_tm27_intr(void)
 {
   rtems_status_code sc = arm_gic_irq_generate_software_irq(
     ARM_GIC_TM27_IRQ_HIGH,
-    ARM_GIC_IRQ_SOFTWARE_IRQ_TO_SELF,
-    0
+    ARM_GIC_IRQ_SOFTWARE_IRQ_TO_ALL_IN_LIST,
+    1U << (arm_cp15_get_multiprocessor_affinity() & 0xff)
   );
   assert(sc == RTEMS_SUCCESSFUL);
 }